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AR# 31780

10.1 ChipScope Pro - Master Xilinx Answer for ChipScope 10.1 and Service Packs

Description

Keywords: LogiCORE, ICON, ILA, ATC2, VIO, SIOTK, IBERT, Analyzer, Inserter, Logic, JTAG

Master Xilinx Answer for ChipScope 10.1.

Solution

(Xilinx Answer 31725) 10.1 ChipScope Pro, IBERT - Differential output swing is limited to 600 mV
(Xilinx Answer 31720) 10.1 ChipScope Pro, IBERT - The number of errors on my unlinked channel is greater than the number of bits received
(Xilinx Answer 31726) 10.1 ChipScope Pro, IBERT - Change of OOBDETECT_THRESHOLD_* to 110 for Virtex-5 GTP and GTX
(Xilinx Answer 31723) 10.1 ChipScope Pro, IBERT - What is the maximum supported Frequency for reflck in GTX IBERT design?
(Xilinx Answer 31719) 10.1 ChipScope Pro - IBERT - FXT sweep test results cannot be modified
(Xilinx Answer 31305) 10.1 ChipScope Pro IBERT - PRBS Data generated by the Virtex-4 IBERT core is inverted for PRBS-23/31
(Xilinx Answer 31184) 10.1 ChipScope Pro iBERT - "ERROR:NgdBuild:32 - Cannot open input file "<file_name>.ucf". "
(Xilinx Answer 31202) 10.1 ChipScope Pro iBERT - There are incorrect bit locations for PMA_RX_CFG_*
(Xilinx Answer 31452) 10.1 ChipScope Pro IBERT - When I open the cable, I am asked to update my DRP settings even though the design is unchanged
(Xilinx Answer 31199) 10.1 ChipScope Pro - IBERT - Wrapper template always includes maximum number of transceiver pins regardless of number of channels selected
(Xilinx Answer 31384) 10.1 ChipScope IBERT - LVDS_DCI_25 is not available for selection as the IO standard on my clock input pin
(Xilinx Answer 30822) 10.1 ChipScope Pro IBERT - Is the Virtex-5 SX240T supported for the IBERT core?
(Xilinx Answer 30823) 10.1 ChipScope Pro IBERT - Change to the GTP/GTX RX Coupling description
(Xilinx Answer 30828) 10.1 ChipScope Pro IBERT - When I use the Parameter Sweep feature, the ".csv" file misnumbers the first iteration and skips the last iterations
(Xilinx Answer 30473) 10.1 ChipScope iBERT Core generator - When generating an iBERT core, a "ERROR:NgdBuild:28 - Top-level input design file..." message appears
(Xilinx Answer 31435) 10.1 ChipScope Pro - When I have ChipScope Inserter or Analyzer open, Project Navigator does not detect updates to my sources
(Xilinx Answer 31306) 10.1 ChipScope Pro - When I attempt to run ChipScope Inserter command line, I see: "java.awt.HeadlessException:" or a similar message
(Xilinx Answer 30827) 10.1 ChipScope Pro - Cannot launch Agilent Serial Link Optimizer from the Analyzer GUI
(Xilinx Answer 30824) 10.1 ChipScope Pro - In the Analyzer GUI, the closing "x" in Configure Dialog does not work
(Xilinx Answer 31713) 10.1 ChipScope Pro - Does ChipScope Pro support the Virtex-5 TXT family?
(Xilinx Answer 31727) 10.1 ChipScope Pro - Does ChipScope support the Virtex-5 FX200T?
(Xilinx Answer 31596) 10.1 ChipScope Pro - Can I use a BSCAN in my design when I insert ChipScope cores? How do I tell ChipScope to use a specific BSCAN primitive?
(Xilinx Answer 31307) 10.1 ChipScope Pro - "ERROR:sim - Error: XST failed for chipscope_ila_v1_02_a. ERROR:Xst:1312 - Loop has iterated 64 times. Use "set -loop_iteration_limit XX" to iterate more"
(Xilinx Answer 31528) 10.1 ChipScope Pro - Where is the ChipScope CORE Generator tool?
(Xilinx Answer 31200) 10.1 ChipScope Pro - Where is the option to Disable BUFG insertion on my JTAG clock for the ICON?
(Xilinx Answer 30983) 10.1 ChipScope Pro - When I use CseJTAG and the CseJtag_shiftDeviceDR, the last bit shifted out is always 0
(Xilinx Answer 30829) 10.1 ChipScope Pro - When using the IBERT parameter sweep console, I receive "Error on get Sweep Test Result file" and some of my results are missing
(Xilinx Answer 30783) 10.1 ChipScope - Running setup -autoupgrade on Linux results in "No Xilinx products can be found in the registry"
(Xilinx Answer 30784) 10.1 ChipScope - Software Updates/Service Packs are not available when running XilinxUpdate
(Xilinx Answer 30963) 10.1 ChipScope Pro - Various match unit types and counter selections made in the Core Inserter are not reflected in the Analyzer
(Xilinx Answer 30945) 10.1 ChipScope Pro/ISE - DEBUG (dpm_chSNEditOperationWithUpdate): processing Edit request for SourceDUNode
(Xilinx Answer 30474) 10.1 ChipScope Pro - Running ChipScope Core Inserter or analyzer from ISE results in "Error: Unable to find ChipScope Exe at <File Path>"
(Xilinx Answer 30283) 10.1 ChipScope Pro/ISE - "ERROR:LIT:266/267/296/407/409/456" or "ERROR:Maplib" occurs during implementation if ChipScope cores are present
(Xilinx Answer 30284) 10.1 ChipScope Pro - ILA tool in FPGA Editor cannot find my ChipScope ILA Core
(Xilinx Answer 30231) 10.1 ChipScope Pro - "Driver installation failed. Please check the <Install Destination Directory>/.xinstall/install.log for more information on the cause of the failure."
(Xilinx Answer 30232) 10.1 ChipScope Pro - ISE cannot find ChipScope Pro tools
(Xilinx Answer 30227) 10.1 ChipScope Pro - Eval Version shows up as Full version for ChipScope Pro and the SIOTK
(Xilinx Answer 30202) 10.1 ChipScope Pro - Core Inserter will not launch from Shortcut
(Xilinx Answer 30200) 10.1 ChipScope Pro - Touching any key on keyboard causes hard application error in smartheap SHSMP.DL
(Xilinx Answer 30230) 10.1 ChipScope Pro - ChipScope cannot find cable drivers when using the cs_server and issues error: "ERROR: Failed to open Xilinx Platform USB Cable"
(Xilinx Answer 30223) 10.1 ChipScope Pro - Release Notes and Known Issues
(Xilinx Answer 30472) 10.1 ChipScope Pro - Creating PlanAhead project when source files contain ChipScope cores results in "FATAL_ERROR:Portability:basutformat.c:146:1.19"
(Xilinx Answer 31195) 10.1 ChipScope Pro - Does ChipScope support multiple Platform Cable USB connections?
(Xilinx Answer 25240) 10.1 ChipScope Pro - "ERROR:ChipScope:No Xilinx Environment Found!"
(Xilinx Answer 31691) 10.1.03 ChipScope Pro - ERROR: ChipScope Insertion failed
(Xilinx Answer 31428) 10.1 ChipScope Pro - "ERROR: sim - DoQuickCopy : Could not execute xlicmgr.exe"
(Xilinx Answer 31427) 10.1 ChipScope Pro - The CPU usage is high and my PC slows down when I perform a capture in the Analyzer on my ILA
(Xilinx Answer 31714) 10.1 ChipScope Pro, Inserter - NGCBuild errors are not appearing in Project Navigator
(Xilinx Answer 31715) 10.1 ChipScope Pro, Inserter - When launching the Inserter, I see Stack dump messages
(Xilinx Answer 31724) 10.1 ChipScope Pro, Inserter - Inserter fails to launch with "java.lang.NullPointerException" messages
(Xilinx Answer 25281) 10.1/9.2i ChipScope Pro Core Inserter - Core Inserter does not open when I double-click the ".cdc" file in ISE
(Xilinx Answer 30985) 10.1 ChipScope Pro Inserter - "WARNING:Par:288 - The signal <signal_name > has no load. PAR will not attempt to route this signal."
(Xilinx Answer 31198) 10.1 ChipScope Pro Analyzer - In VIO Console, switching output types from button to text field disables output value
(Xilinx Answer 31197) 10.1 ChipScope Pro Analyzer - When I import an FPGA Editor-produced CDC, my data and trigger ports in ILA are not named correctly
(Xilinx Answer 31201) 10.1 ChipScope Pro Analyzer - Virtex-4 XC4VFX40 IDCODE not recognized correctly
(Xilinx Answer 31721) 10.1 ChipScope Pro, Analyzer - I cannot delete multiple signals from a bus
(Xilinx Answer 31160) 10.1.01i ChipScope Pro Analyzer - Importing vio.cdc file Analyzer does not change all the signal names in VIO console
(Xilinx Answer 30826) 10.1 ChipScope Pro - The Analyzer IBERT console "Edit Ports" dialog tab is incorrectly labeled "Attribute name"
(Xilinx Answer 30825) 10.1 ChipScope Pro Analyzer - Changing a VIO output type from "text" to "toggle" also changes the value
(Xilinx Answer 31711) 10.1 ChipScope Pro, CORE Generator - Edits to "Data Port Width" are lost when "Data Same As Trigger" setting is modified
(Xilinx Answer 31710) 10.1 ChipScope Pro, CORE Generator - Changing number of match units does not flag error when total is greater than 16
(Xilinx Answer 31712) 10.1 ChipScope Pro, CORE Generator - ERROR:NGDBuild:756 - "<path>/<filename>.ncf" Line xx 3: Could not find net(s) '<net_name>' in the design
(Xilinx Answer 31196) 10.1 ChipScope - CORE GENERATOR - Options for Icon/ILA/VIO automotive and hi-rel families are grayed out and unavailable for generation
(Xilinx Answer 30203) 10.1 ChipScope Pro, LogiCORE ICON (ChipScope Pro - Integrated Controller) - When I generate my ICON Core, I see "ERROR:NgdBuild:756 - "../cs/icon.ncf" Line 1: Could not find net(s)"
(Xilinx Answer 30801) 10.1 ChipScope Pro Install - Service Pack Release Notes (README)
(Xilinx Answer 30217) 10.1 iMPACT, ChipScope, SysGen, XMD - Platform Cable USB cable disconnects with "DeviceDetach: received detach for device handle 0x......." message
(Xilinx Answer 31746) 10.1 ChipScope Pro - When I generate my ATC2 Agilent using the Inserter flow, the pins are locked to incorrect locations
(Xilinx Answer 31621) 10.1 EDK - Why am I unable to regenerate my EDK system after making modifications to the ChipScope core?
(Xilinx Answer 31697) 10.1.03 ChipScope Pro GTP SIOTK - Errors in the middle of eye during IBERT parameter sweep
(Xilinx Answer 30856) 10.1 CORE Generator - ChipScope core is not created if EDIF is selected as netlist output type
(Xilinx Answer 31686) 10.1 Partitions - ChipScope Generator ILA and ICON instantiations only work in the top-level module
(Xilinx Answer 31656) 10.1 EDK - The agilent_atc2 core cannot find the ChipScope installation
(Xilinx Answer 31230) 10.1 EDK - Support for Automotive parts in the ChipScope PLBv46 IBA
(Xilinx Answer 30643) 10.1 EDK - "ERROR:: Cannot locate library chipscope_plbv46_iba_v1_01_a"
(Xilinx Answer 30642) 10.1 EDK - Why does the chipscope_icon_v1.02a use BUFGs even though I set use_bufg = false?
(Xilinx Answer 29857) 10.1 EDK - How do I connect signals to the data port of ChipScope Pro ILA Core?
(Xilinx Answer 23991) 10.1 EDK - When using ChipScope in an EDK design, I find that EDK always uses the last ChipScope version installed
(Xilinx Answer 23633) 10.1 EDK - How do I insert ChipScope when my EDK project is a sub-system?

AR# 31780
Date Created 10/09/2008
Last Updated 10/09/2008
Status Active
Type General Article