AR #31794 - Platform Flash XL, EDK Support - How do I access the Platform Flash XL from an EDK design?
Platform Flash XL, EDK Support - How do I access the Platform Flash XL from an EDK design?
| AR# | 31794 |
| Part | Config-BPI |
| Last Modified | 2009-07-14 00:00:00.0 |
| Status | Active |
| Keywords | opb, emc, flash, writer, 128 |
Description
Keywords: opb, emc, flash, writer, 128
How can I design read and write out of the Platform Flash XL?
The EDK tool set can be used to talk to the Platform Flash XL by following this Answer Record. EDK is required because the External Memory Controller (XPS_EMC) Core is used to manage addressing during communication. If EDK is not used in the design, a small EDK design can be built and instantiated in the HDL code.
The HiTech Global Virtex-5 FX70T HTG-DDR3 board is available at:
http://www.hitechglobal.com/boards/v5ddr3_pcie.htm
This documentation should also be used in conjunction with the following Xilinx Application Notes:
(Xilinx XAPP1100) - MultiBoot with Virtex-5 FPGAs and Platform Flash
(Xilinx XAPP973) - Indirect Programming of BPI PROMs with Virtex-5 FPGAs
Solution
The current version of the XIL_FLASH libaries only support a single bank architecture for reading and writing to the flash. The single bank architecture only has one status register for the entire device.The Platform Flash XL is a multi-bank architecture and provides users with a status register for each bank. This expanded capability is not currently supported by the XIL_FLASH libraries.
To add programming support for the flash, include the XPS_EMC core in the design. There is a sample ".mhs" file in the patch files which outline the required hardware parameters and setup for the flash.
Next, the xil_flash libraries need to be updated to the version in the attached ZIP file. This version of the xil_flash libraries will support the multi-bank architecture of the Platform Flash XL. The updated drivers also support issuing the asynchronus read command required before any read or write commands are issued.
The attached xil_flash library can be used as a replacement for the existing library and includes the full api, as well as example code:
ftp://ftp.xilinx.com/pub/utilities/fpga/31794.zip
NOTE: If IPROG is issued while the device is still in ASYNC mode, the system might not configure properly.