UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 31801

MIG v2.3 - Spartan-3A Starter Kit: When running the ISE project output by create_ise.bat, Translate fails with ERROR:ConstraintSystem:59

Description

The MIG output includes a create_ise.bat script file in the "par" directory that can be run to generate an ISE project with the MIG output files.

For the MIG v2.3 Spartan-3A Starter Kit design, running Translate with the created project will result in errors similar to the following: 

ERROR:ConstraintSystem:59 - Constraint <INST "main_00/top0/data_path0/data_read0/strobe1_n/fifo_bit4" LOC = SLICE_X0Y77;> [vhdl_bl4.ucf(590)]:
INST "main_00/top0/data_path0/data_read0/strobe1_n/fifo_bit4" not found. Please verify that:  
1. The specified design element actually exists in the original design.  
2. The specified object is spelled correctly in the constraint source file.  


What is causing this error and how can I work around it?

Solution

These errors occur because the vhdl_bl3_ram8d_1.vhd file has not be added to the ISE project.

This is a bug in the create_ise.bat script.

To work around this issue, manually add the source file vhdl_bl3_ram7d_1.vhd to the ISE project.

This source file can be found in the "rtl" directory.

Once this change is made, Translate will complete successfully.  

This issue will be resolved in MIG 3.0.
AR# 31801
Date Created 10/15/2008
Last Updated 08/18/2014
Status Active
Type General Article
Devices
  • Spartan-3A
IP
  • MIG
Boards & Kits
  • Spartan-3A Starter Kit