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AR# 31802

MIG v2.3 - Virtex-5 DDR2 Multi-Controller: Example_Design and User_Design pinouts do not match

Description

When generating a Virtex-5 FPGA DDR2 multi-controller design, the pinout is different in the provided example design UCF and the user design UCF.

Why is the pinout different and when will this be resolved?

Solution

The current MIG pin algorithm allocates the user_design and example_design pinouts for all of the controllers sequentially.

The pinouts for Controller0 will match, but from the second controller onwards, they will not.

This is because of the additional system control signals for the example_design.    

Starting with MIG 3.0, a new pin algorithm will be used.

This will allocate the pinout for the example_design and then copy the same pins to the user_design and delete the additional system control signals.

This will ensure that the pinouts for the example_design and user_design match.
AR# 31802
Date Created 10/15/2008
Last Updated 12/04/2014
Status Active
Type General Article
Devices
  • Virtex-5 FXT
  • Virtex-5 LX
  • Virtex-5 LXT
  • More
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Less
IP
  • MIG