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AR# 31806

10.1 EDK - PLB Master registers do not update correctly in the BFM simulation flow

Description

The PLB BFM master model does not update the internal generic registers.

When attempting to read() from a memory location and specifying to load a register, and then a memory is updated with that register, the register is not available.

For example:

mem_init(addr=00000000, data=ABCDEF01_DEADBEEF)

mem_init(addr=00000008, data=FFFFFFFF_EEEEEEEE)

write(addr=00000000,size=0000,be=11110000)

read(addr=00000000,size=0000,be=11110000,data=R2)

mem_update(addr=00000008,data=R2)

write(addr=00000008,size=0000,be=11110000)

Instead of the final write() placing ABCDEF01 on the bus, 00000000 is written instead.

Solution

Xilinx has not found a resolution to this issue with the VHDL version of the IBM Toolkit. Xilinx recommends that you do not use the BFM registers.

The registers are used to store data to be used for perhaps other reads and writes. Since these are not available, it is not possible to store random values that might be read from a slave. The only way a read will work is if the data is known beforehand and this data is then used in the mem_update for that address. If random data is expected from a slave, it is not possible to verify the correctness of the data received.

AR# 31806
Date Created 10/23/2008
Last Updated 12/15/2012
Status Active
Type General Article