In the design OFDDRRSE and OBUFDS are connected in series when implementing the design, an error message is shown:
ERROR: LIT: 156 - The O pin of OBUF symbol "OFDDRRSE_inst/OBUF1" (output signal=q1) does not have a valid load. It is driving: pin I of OBUFDS symbol "OBUFDS_inst" (output signal=OB), pin SNK of Output PAD symbol "q1".
The OFDDRRSE component has OBUF in it, and when OBUFDS is connected in series with this component an error message is shown saying that two OBUF cannot be in series.
To work around this issue, use the FDDRRSE primitive and then connect the OBUFDS. This will implement the design successfully.
FDDRRSE primitive is not documented in Virtex-II Pro Libraries Guide for HDL Designs <http://toolbox.xilinx.com/docsan/xilinx10/books/docs/virtex2p_hdl/virtex2p_hdl.pdf>
But FDDRRSE primitive is listed in Virtex-II Pro Libraries Guide for Schematic Designs <http://toolbox.xilinx.com/docsan/xilinx10/books/docs/virtex2p_scm/virtex2p_scm.pdf>