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AR# 31832

Constraints - Is there a way to globally set IOSTANDARD constraints and not have to set it for each individual I/O?

Description

The ISE and Vivado tools set default I/O standards automatically. Is there a way to change to other I/O standards?

Solution

Vivado:

The following Tcl command will set all non-MGT pins to an IOSTANDARD (in this case LVCMOS18):

set_property IOSTANDARD LVCMOS18 [get_ports -of_objects [get_iobanks -filter { BANK_TYPE !~  "BT_MGT" }]]

ISE Design Suite:

Add the below constraint in the UCF file:

NET "*" IOSTANDARD = USER_DEFAULT_IOSTANDARD;

This constraint will overwrite the I/O standard constraints in XCF or HDL code and set all of the I/Os to USER_DEFAULT_IOSTANDARD.

If there are other IOSTANDARDs in the design, you need to add corresponding IOSTANDARD constraints to overwrite this global one. For example, if assigning the USET_DEFAULT_IOSTANDARD is a single-ended standard and there are some differential I/Os in the design, there would be an error during the MAP process; you must manually specify the correct I/O standard in the UCF for those differential I/Os.

The DEFAULT IOSTANDARD constraints will not be supported.


Note: In the latest ISE 13.x software, there have been changes to the propagation rules of constraints on nets. 

This new propagation rules might prevent the above constraint from working as expected. The above constraint might provide inconsistent results on your given design.

The use of a wildcard to specify an IOSTANDARD is not ideal, because the wildcard will match to internal nets. Internal nets do not support I/O Standard constraints. It is recommended to specify the IOSTANDARD for every I/O in your design.

The DEFAULT constraint does support DRIVE and SLEW; however, this does not apply to IOSTANDARD.

WARNING:NgdBuild:1421 - 'DEFAULT IOSTANDARD' constraint in file 'example_top.ucf' at line '41' will not globally set the iostandard for the design.

A suggested way to specify each I/O is to use the "Back Annotate Pin Locations" option under the PAR process. This lists out all of the pins locked down from a successful PAR run, and you can add IOSTANDARDs to each one.


Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
37214 Virtex-6 FPGA Design Assistant - Troubleshoot common block RAM/FIFO problems N/A N/A
AR# 31832
Date Created 10/21/2008
Last Updated 11/21/2016
Status Active
Type General Article
Tools
  • ISE Design Suite - 13.1
  • ISE Design Suite - 13.2
  • ISE Design Suite - 13.3
  • More
  • ISE Design Suite - 13.4
  • ISE - 10.1
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • ISE Design Suite - 11.3
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2
  • ISE Design Suite - 12.3
  • ISE Design Suite - 12.4
  • Vivado Design Suite
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