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AR# 31834

Serial RapidIO v5.1 - Generation of PHY-only core fails with "HDLCompilers:87" error


When generating a PHY-only design (that is, the Logical Layer Core is not also selected on page 1 of the customization GUI) for the Serial RapidIO v5.1 Core, the following error message occurs in CORE Generator, and the core is not generated:

ERROR:sim - Error: XST failed for rio_buffer. ERROR:HDLCompilers:87 - "C:\Data\coregen_IP3_K\tmp\_cg/_bbx/srio_v5_1/buffer/rx_buffer.v" line 732 Could not find module/primitive 'EVAL'


A patch is available for the Serial RapidIO v5.1 core to fix this issue. See (Xilinx Answer 31573) for details.

Revision History

10/21/2008 - Initial Release
11/11/2008 - Updated AR with patch information

AR# 31834
Date Created 10/21/2008
Last Updated 12/15/2012
Status Active
Type General Article