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AR# 31855

12.1 Release Note - Timing - Why do I see Component Switching Limit values change in my timing report for PLLs and DCMs

Description

Why do I see Component Switching Limit (pulse limit) values change in my timing report for PLLs and DCMs? I have changed the frequency of my clock, but I did not change any of the modes of operation. I thought these limits were a static limitation of the hardware?

Solution


The pulse limit is a static value for frequency checks. However, it is dynamic for different duty cycles.
From the data sheet for this device, the DCM has a Duty Cycle Input Tolerance (DCIT) as follows (this is also from the data sheet, and generally follows normal DCM switching limit tables):
[50]-100 MHz allowable DCIT 30/70
[100]-200 MHz allowable DCIT 40/60
From the examples below, the following limits exist:
50 MHz Pulse limit is 3.000 ns
135 MHz Pulse limit is 2.400 ns
Following the data sheet DCIT at 50 MHz:
20 ns (50 MHz) * 30% (of the cycle) = 3.000 ns
Following the data sheet DCIT at 135 MHz:
7.407 ns (135 MHz) * 40% (of the cycle) = 2.963 ns
This difference is that the data sheet is more pessimistic when reporting these values, and the timing report shown below is more optimistic and realistic. The 3.00 ns value directly correlates to the data sheet, while the 135 MHz value in the data sheet is more pessimistic.
Example for 50 MHz clock and 50/50 duty cycle:
--------------------------------------------------------------------------------
Slack: 14.000 (period - (min low pulse limit / (low pulse / period)))
Period: 20.000
Low pulse: 10.000
Low pulse limit: 3.000
Physical resource: dcm_clk0_inst/DCM_INST/DCM_ADV/CLKIN
Logical resource: dcm_clk0_inst/DCM_INST/DCM_ADV/CLKIN
Location pin: DCM_ADV_X0Y0.CLKIN
Clock network: dcm_clk0_inst/CLKIN_IBUFG_OUT
--------------------------------------------------------------------------------
Slack: 14.000 (period - (min high pulse limit / (high pulse / period)))
Period: 20.000
High pulse: 10.000
High pulse limit: 3.000
Physical resource: dcm_clk0_inst/DCM_INST/DCM_ADV/CLKIN
Logical resource: dcm_clk0_inst/DCM_INST/DCM_ADV/CLKIN
Location pin: DCM_ADV_X0Y0.CLKIN
Clock network: dcm_clk0_inst/CLKIN_IBUFG_OUT
--------------------------------------------------------------------------------
Example for same design as above, but with a clock at 135 MHz and 50/50 duty cycle:
--------------------------------------------------------------------------------
Slack: 2.606 (period - (min low pulse limit / (low pulse / period)))
Period: 7.406
Low pulse: 3.703
Low pulse limit: 2.400
Physical resource: dcm_clk0_inst/DCM_INST/DCM_ADV/CLKIN
Logical resource: dcm_clk0_inst/DCM_INST/DCM_ADV/CLKIN
Location pin: DCM_ADV_X0Y0.CLKIN
Clock network: dcm_clk0_inst/CLKIN_IBUFG_OUT
--------------------------------------------------------------------------------
Slack: 2.606 (period - (min high pulse limit / (high pulse / period)))
Period: 7.406
High pulse: 3.703
High pulse limit: 2.400
Physical resource: dcm_clk0_inst/DCM_INST/DCM_ADV/CLKIN
Logical resource: dcm_clk0_inst/DCM_INST/DCM_ADV/CLKIN
Location pin: DCM_ADV_X0Y0.CLKIN
Clock network: dcm_clk0_inst/CLKIN_IBUFG_OUT
--------------------------------------------------------------------------------
AR# 31855
Date Created 04/07/2009
Last Updated 12/15/2012
Status Active
Type General Article
Tools
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