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AR# 31856

11.x XST - "WARNING:Xst:1710/1895 - This FF/Latch will be trimmed during the optimization process."

Description

Keywords: XST, synthesis, synthesize, trimmed, Verilog, Xst:1710 , Xst:1895

When I use XST to synthesize the following HDL :

Verilog codes:
reg [4:0] counter;
always@(posedge clk)
begin
counter <= counter +1;
dout[32- counter -1] <= din;
end

Warning messages similar to the following are displayed:

"WARNING:Xst:1710 - FF/Latch <dout_30> (without init value) has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dout_31> (without init value) has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process."

How can I resolve this problem?

Solution

This issue is fixed for new architectures (Virtex-6 and later).

If you are using older devices, the code can be rewritten as follows:

dout[32- {0,counter} -1] <= din;
AR# 31856
Date Created 10/30/2008
Last Updated 12/13/2009
Status Active
Type General Article