UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 31858

LogiCORE 3GPP LTE Turbo Decoder v1.0 - Why is there a difference between the C Model simulation and the core output for maximum input values to the decoder?

Description

Why is there a difference between the C Model simulation and the core output for maximum input values to the decoder?

Solution

When just using the maximum input values for the tail bits, the C model and the decoder will differ in the bit output. The C model is correct. At all other times, the output of the core is correct. This minor issue will be fixed in a future release of the core. 

 

Please see (Xilinx Answer 30630) for a detailed list of LogiCORE 3GPP LTE Turbo DecoderRelease Notes and Known Issues.

AR# 31858
Date Created 10/30/2008
Last Updated 05/21/2014
Status Archive
Type General Article