Virtex-4/-5 Embedded Tri-Mode Ethernet MAC - Problems switching from 10/100 Mb/s to 1G GMII operation

Description

The internal clock mux in the Virtex-4 or Virtex-5 FPGA Embedded TEMAC requires a falling edge on the PHYEMAC#MIITXCLK input to correctly switch the GMIIMIICLKOUT from a 10/100 clock to the 1G clock. This means that if the MII TX CLK from the PHY is not toggling, the TEMAC will not switch from 10 or 100 Mb/s operation to 1G operation correctly.

Solution

Please be aware that some tri-speed PHYs can stop the MII TX CLK in 1G GMII mode, but this is not always the case. For example, the Marvell 88E1111 PHY on the ML40X/50X demo boards defaults to having the PHY output the MII TX CLK in 1G mode. Therefore, this issue does not occur in the default GMII configuration of these boards.

This issue only affects the Virtex-4 and Virtex-5 FPGA Embedded TEMAC when using the standard clocking for tri-speed GMII in the following cores: 

• Virtex-4 FPGA Embedded Tri-mode Ethernet MAC Wrapper v4.7 or earlier. 
• Virtex-5 FPGA Embedded Tri-mode Ethernet MAC Wrapper v1.5 or earlier. 
• XPS_LL_TEMAC v1.01b or earlier with the hard TEMAC blocks. 

This is not an issue in the following cases: 

• when using the soft Tri-Mode Ethernet MAC. 
• when using any other Physical interface, such as RGMII or SGMII. 
• when the internal clock muxes are not used in GMII mode (see work-around below). 
• when the MII TX CLK from the PHY does not stop. 

To work around the issue: 

1. The PHY can be configured to not stop the MII TX CLK from the PHY. 
2. Use the Clock Enable or Byte-PHY tri-speed GMII clocking schemes provided in UG074 and UG194. These use external clock muxes and therefore, the problem is not seen.  

This issue is fixed in 11.1 for the Virtex-5 FPGA Embedded Tri-mode Ethernet MAC wrapper by using external clock muxes.  

This issue is fixed in 12.1 for the Virtex-4 FPGA Embedded Tri-mode Ethernet MAC wrapper by using external clock muxes.