After the core is released from reset and the DCM has locked, invalid data is sent out on XGMII_TXD for a couple clock cycles.
The invalid data transmitted is like a remote fault, except that the bytes/nibbles have been swapped on the XGMII_TXD, but not on XGMII_TXC. During the invalid sequence:
XGMII_TXD is "9C0000019C000001" and XGMII_TXC is "00010001"
This issue only occurs directly after the reset. This is scheduled to be fixed in the next release of the core.