We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 31884

11.1 EDK - What are the different implementation options between an XPS flow versus an ISE flow?


When I have an EDK project instantiated in an ISE project, what different implementation options will be used?


The notable differences between EDK and ISE are:

EDK: map -pr b -timing; par -ol high

ISE: map -pr off; par -ol std

To ensure that the EDK cores perform as intended when inside of an ISE design, change the ISE settings to match the EDK settings that are listed above.

NOTE: The -timing switch is on by default for Virtex-5, so there is no need to add this switch when targeting Virtex-5 devices.

AR# 31884
Date Created 11/03/2008
Last Updated 12/15/2012
Status Active
Type General Article