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AR# 31895

Virtex-5 FPGA IOLOGIC/IODELAY - "ERROR:PhysDesignRules:796 - Component ISERDES_NODELAY_inst has routethru"

Description

Keywords: BitGen, ISERDES, routethrough

When a clock is used as an input to an ISERDES_NODELAY and is used as an input to an IDELAY, the following BitGen error occurs:

"ERROR:PhysDesignRules:796 - Component ISERDES_NODELAY_inst has routethru conflicts."

Solution

The problem was found to be with the modeling of the route-thru in the software.

To work around this issue, replace ISERDES_NODELAY and IDELAY with an ISERDES. The ISERDES was a primitive in the Virtex-4 architecture. You can use the instantiation from the Virtex-4 FPGA Libraries Guide or Language Template.

Following is the ISERDES instantiation from the ISE Language Templates:

ISERDES_inst : ISERDES
generic map (
BITSLIP_ENABLE => FALSE, -- TRUE/FALSE to enable bitslip controller
-- Must be "FALSE" in interface type is "MEMORY"
DATA_RATE => "DDR", -- Specify data rate of "DDR" or "SDR"
DATA_WIDTH => 4, -- Specify data width - For DDR 4,6,8, or 10
-- For SDR 2,3,4,5,6,7, or 8
INTERFACE_TYPE => "MEMORY", -- Use model - "MEMORY" or "NETWORKING"
IOBDELAY => "NONE", -- Specify outputs where delay chain will be applied
-- "NONE", "IBUF", "IFD", or "BOTH"
IOBDELAY_TYPE => "DEFAULT", -- Set tap delay "DEFAULT", "FIXED", or "VARIABLE"
IOBDELAY_VALUE => 0, -- Set initial tap delay to an integer from 0 to 63
NUM_CE => 2, -- Define number or clock enables to an integer of 1 or 2
SERDES_MODE => "MASTER") --Set SERDES mode to "MASTER" or "SLAVE"
port map (
O => O, -- 1-bit output
Q1 => Q1, -- 1-bit output
Q2 => Q2, -- 1-bit output
Q3 => Q3, -- 1-bit output
Q4 => Q4, -- 1-bit output
Q5 => Q5, -- 1-bit output
Q6 => Q6, -- 1-bit output
SHIFTOUT1 => SHIFTOUT1, -- 1-bit output
SHIFTOUT2 => SHIFTOUT2, -- 1-bit output
BITSLIP => BITSLIP, -- 1-bit input
CE1 => CE1, -- 1-bit input
CE2 => CE2, -- 1-bit input
CLK => CLK, -- 1-bit input
CLKDIV => CLKDIV, -- 1-bit input
D => D, -- 1-bit input
DLYCE => DLYCE, -- 1-bit input
DLYINC => DLYINC, -- 1-bit input
DLYRST => DLYRST, -- 1-bit input
OCLK => OCLK, -- 1-bit input
REV => '0', -- Must be tied to logic zero
SHIFTIN1 => SHIFTIN1, -- 1-bit input
SHIFTIN2 => SHIFTIN2, -- 1-bit input
SR => SR -- 1-bit input
);
AR# 31895
Date Created 11/07/2008
Last Updated 07/28/2009
Status Active
Type General Article