Solution

The SDRAM PHY uses a system-synchronous capture scheme where the memory must respond within a single FPGA clock cycle. This is different from the MIG-based and static PHYs, where the read capture timing is calibrated for maximum margin using IDELAYs or DCM phase shifting, respectively.

The simple capture scheme of the SDRAM PHY will fail if the memory, with its forwarded clock from the FPGA, is not able to respond and meet the setup time of the FPGA inputs during a read. The FPGA read logic samples the data on the internal FPGA clock.

If problems occur, consider replacing the forwarded clock output from MPMC with an adjustable DCM phase-shifted clock. Note that the default MPMC SDRAM PHY inverts the forwarded clock to memory, without a IOB DDR register, and then also samples the read data on the falling edge of MPMC_Clk0. Thus, the CLK180 output of the DCM is the best candidate to be sent to memory, although it will use an additional BUFG for the CLK0 feedback loop. It is suggested to use a slightly negative phase shift to improve the read transaction setup time. However, too much of a negative phase shift could cause hold violations on the write path from the FPGA to the memory chip, since the memory runs off of the forwarded clock for both writes and reads. A phase shift of "0" using the CLK180 output of the DCM is equivalent to the current implementation of MPMC, assuming the DCM CLKIN clock is equivalent to the clock generating MPMC_Clk0.

Work-around details:

On the MPMC instance, the SDRAM_Clk port must be connected to an unused net to prevent DRC errors.

PORT SDRAM_Clk = unused_net

The dcm_module pcore can be used to adjust the output clock to the memory. An example follows:

BEGIN dcm_module
PARAMETER INSTANCE = dcm_module_0
PARAMETER HW_VER = 1.00.d
PARAMETER C_CLKOUT_PHASE_SHIFT = FIXED
PARAMETER C_CLK0_BUF = TRUE
PARAMETER C_CLK180_BUF = TRUE
PARAMETER C_PHASE_SHIFT = -32
PORT CLKIN = dcm_clk_s
PORT CLK180 = fpga_0_SDR_SDRAM_CUSTOM_SDRAM_Clk
PORT LOCKED = dcm_module_0_LOCKED
PORT CLK0 = dcm_module_0_CLK0
PORT CLKFB = dcm_module_0_CLK0
END


This issue has been fixed in MPMC v5.00.a of EDK 11.1 and later by changing the read capture logic to be similar to the static PHY. The SDRAM PHY in MPMCv5.00.a and later will use the static and can use the software calibration example provided as part of the MPMC software driver. All SDR SDRAM MPMC users are encouraged to migrate to MPMCv5.00.a and later for maximum memory stability.