We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 31912

LogiCORE Ethernet PCS/PMA 1000BASE-X or SGMII and Virtex-5 Embedded Tri-mode Ethernet MAC - 1000BASE-X and SGMII interfaces using DCMs should have additional BUFG inserted for optimal routing


All of the Virtex-5 GTX 1000BASE-X and SGMII example design clocking schemes use a DCM. A DCM is also used in the clocking scheme for the Virtex-5 Embedded Tri-mode Ethernet MAC GTP 1000BASE-X 16-bit client interface option. Currently, when a DCM is used, the REFCLKOUT clock signal is routed to a DCM without being put on global routing. For optimal performance, the REFCLKOUT should be routed to a BUFG before going to the DCM. This is not applicable to clocking schemes not using a DCM.


To use the most optimal routing, a BUFG can be added between the REFCLKOUT of the GTP/GTX and the CLKIN of the DCM.  


Applicable Cores and interfaces are: 


LogiCORE Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 and earlier:  

GTX 1000BASE-X and SGMII Interfaces 


Virtex-5 Embedded Tri-mode Ethernet MAC Wrapper v1.5 and earlier: 

GTX 1000BASE-X and SGMII Interfaces 

GTP 1000BASE-X 16-bit Client Interface 


XPS_LL_TEMAC v1.01b:  

GTX 1000BASE-X and SGMII interfaces 


This additional BUFG will be added in the next releases of these cores due out in 11.1 IPUpdate1.

AR# 31912
Date Created 11/14/2008
Last Updated 05/23/2014
Status Archive
Type General Article