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AR# 31925

Virtex-5 FPGA GTP RocketIO - Transmit data errors detected on the far end receiver due to unusual errors on the TX serial lines


If you use the Virtex-5 FPGA GTPs, there might be intermittent data errors detected on the far end receiver because of unusual errors on the TX serial lines while in near end PCS or PMA loopback, or K-character transmission errors. However, the data going into the GTP on the TXDATA pins is correct.

What is happening with my design?


To identify if the data errors in your design are related to this issue, the ChipScope toolcan be used to determine if the following conditions exist:
  1. In a design using 8b10b encoding, TXKERR toggles when a valid K-character is presented at TXDATA with TXCHARISK asserted. In most 8b10b encoded systems, K-characters are transmitted periodically, so simply observing if TXKERR asserts should be adequate. The ChipScope tool can be used to monitor TXDATA, TXCHARISK, and TXKERR to verify if TXKERR is occurring on valid TXDATA.
  2. If the communication protocol allows it, verify if the problem exists when using near end PCS or PMA loopback. When in loopback, if the received data matches the transmitted data, then this is not the issue causing errors at the far end receiver. Those issues are most likely some type of signal integrity related problem.
  3. The error can be build dependent, meaning that on one run through the Place and Route, the design might work correctly while on others it could fail without code changes. Using different Place and Route seeds on the same design can be used to identify if the problem is consistent.

If you observethese conditions, please open a WebCase with Xilinx Technical Support. A tactical patch can be made available upon request: http://www.xilinx.com/support/clearexpress/websupport.htm
AR# 31925
Date Created 07/07/2009
Last Updated 08/29/2012
Status Active
Type Known Issues
  • Virtex-5 FXT
  • Virtex-5 LX
  • Virtex-5 LXT
  • More
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Virtex-5Q
  • Less