Keywords: DSP48, column, Virtex-5, Virtex-4, Spartan-3A DSP
When I implement my System Generator for DSP design containing a FIR Compiler block, the following error occurs:
"ERROR:Place:673 - DSP component "../gen_v4_and_v5.gen_dsp48e.dsp48e_v5" is the start of a cascade of DSP components. They need to be placed in correct order into vertically adjacent DSP sites. An issues has been detected with the correct placement of these DSP components. The reason for this issue: The logic does not fit onto the chip in this form.The following components are part of this structure."
This error can occur in designs using the FIR Compiler block in System Generator for DSP, given the following conditions:
- A symmetric coefficient structure is specified.
and
- The number of DSP48 slices required exceeds the number of DSP48 slices in a single column on the given target device.
The FIR Compiler cannot currently support an architecture which optimizes a symmetric coefficient structure by folding the coefficients and using a pre-adder across multiple DSP48 columns.
This error can occur because System Generator for DSP does not check if the FIR Compiler configuration required exceeds the DSP48 slice column height on the device, and might generate a core which cannot be placed on the given device.
To work around this issue, you can either specify the coefficients as non-symmetric, or reduce the number of coefficients.
In 11.2, a more descriptive error message is given explaining the violation.