General LogiCORE IP Video Scaler Issues - (Xilinx Answer 33867) - Design Advisories for MVI (Multimedia, Video, and Imaging) IP including, but not limited to Image Processing Pipeline, Video On-Screen Display, Video DMA, Video Scaler, Video Timing Controller
- (Xilinx Answer 35262) - How do I create scaling coefficients and COE files for the LogiCORE IP Video Scaler?
- (Xilinx Answer 34828) - How do I simulate my Video IP pCore in EDK?
LogiCORE IP Video Scaler v7.01.a - Initial release in ISE 14.3 and Vivado 2012.3 tools
Supported Devices (ISE) - All 7 series
- All Virtex-6
- All Spartan-6
Supported Devices (Vivado)
New Features - Fixed clock domain issues with registers in the AXI4-Lite connection
Resolved ssues (ISE)
Resolved Issues (Vivado) - (Xilinx Answer 47523) - Why do the AXI4-Lite register readbacks fail sometimes in simulation?
- (Xilinx Answer 50909) - 2012.2 Vivado Simulator - Why do I receive errors or data mismatches when I attempt to simulate my IP in Vivado Simulator using the behavioral simulation flow?
- (Xilinx Answer 51232) - Why does my software hang when using the Video Scaler pCore driver in EDK?
Known Issues (ISE) - (Xilinx Answer 52215) - Why does my core fail timing with an Critical Warning?
- (Xilinx Answer 52285) - Why doesn't the INTC_IF interface pin intr_coef_mem_rdbk_rdy and the intr_coef_mem_rdbk_rdy register behave according to the documentation?
- (Xilinx Answer 52289) - Why isn't an interrupt generated, when one of the error bits in the Status register are set?
- (Xilinx Answer 52392) - Why are the Horizontal Shrink Factor (HSF) and the Vertical Shrink Factor (VSF) registers zero when the AXI4-Lite interface is selected?
- (Xilinx Answer 52987) - Software Driver v4.01.a - Why doesn't SDK 14.3 fail to find the Video Scaler Driver v4.01.a?
- (Xilinx Answer 52998) - Why does my s_axis_video_aclk and m_axis_video_aclk inputs get tied to ground in XPS if I do not connect them to my video clock?
Known Issues (Vivado) - (Xilinx Answer 52215) - Why does my core fail timing with an Critical Warning?
- (Xilinx Answer 52285) - Why doesn't the INTC_IF interface pin intr_coef_mem_rdbk_rdy and the intr_coef_mem_rdbk_rdy register behave according to the documentation?
- (Xilinx Answer 52289) - Why does writing to the Status Register fail to clear the Error bits?
- (Xilinx Answer 52392) - Why are the Horizontal Shrink Factor (HSF) and the Vertical Shrink Factor (VSF) registers zero when the AXI4-Lite interface is selected?
- (Xilinx Answer 52987) - Software Driver v4.01.a - Why doesn't SDK 14.3 fail to find the Video Scaler Driver v4.01.a?
LogiCORE IP Video Scaler v7.00.a - Initial release in ISE 14.2 and Vivado 2012.2 tools
Supported Devices (ISE) - All 7 series
- All Virtex-6
- All Spartan-6
Supported Devices (Vivado)
New Features - Inclusion of AXI4Lite clock and reset.
- AXI4Lite - Other domain CDC now to be handled in the core, not the interconnect
Resolved Issues (ISE)
Resolved Issues (Vivado)
Known Issues (ISE) - (Xilinx Answer 47523) - Why do the AXI4-Lite register readbacks fail sometimes in simulation?
- (Xilinx Answer 51232) - Why does my software hang when using the Video Scaler pCore driver in EDK?
- (Xilinx Answer 52285) - Why doesn't the INTC_IF interface pin intr_coef_mem_rdbk_rdy and the intr_coef_mem_rdbk_rdy register behave according to the documentation?
- (Xilinx Answer 52289) - Why does writing to the Status Register fail to clear the Error bits?
- (Xilinx Answer 52392) - Why are the Horizontal Shrink Factor (HSF) and the Vertical Shrink Factor (VSF) registers zero when the AXI4-Lite interface is selected?
Known Issues (Vivado) - (Xilinx Answer 47523) - Why do the AXI4-Lite register readbacks fail sometimes in simulation?
- (Xilinx Answer 50909) - 2012.2 Vivado Simulator - Why do I receive errors or data mismatches when I attempt to simulate my IP in Vivado Simulator using the behavioral simulation flow?
- (Xilinx Answer 51232) - Why does my software hang when using the Video Scaler pCore driver in EDK?
- (Xilinx Answer 52285) - Why doesn't the INTC_IF interface pin intr_coef_mem_rdbk_rdy and the intr_coef_mem_rdbk_rdy register behave according to the documentation?
- (Xilinx Answer 52289) - Why does writing to the Status Register fail to clear the Error bits?
- (Xilinx Answer 52392) - Why are the Horizontal Shrink Factor (HSF) and the Vertical Shrink Factor (VSF) registers zero when the AXI4-Lite interface is selected?
LogiCORE IP Video Scaler v6.00.a - Initial release in ISE 14.1 and Vivado 2012.1 tools
Supported Devices (ISE) - Virtex-7
- Kintex-7
- Artix-7
- Zynq-7000
- Virtex-6
- Spartan-6
Supported Devices (Vivado) - Virtex-7
- Kintex-7
- Artix-7
- Zynq-7000
New Features - ISE 14.1 tools support
- Virtex-7, Kintex-7, Artix-7 and Zynq device support
- AXI4-Stream interface support for the input and output interfaces
- AXI4-Lite bus interface support for the processor interface
Resolved Issues - (Xilinx Answer 32127) - Why do I receive X_ARAMB36 Block RAM memory collisions when simulating the Video Scaler?
- (Xilinx Answer 37094) - Why does intr_output_error assert unexpectedly at the beginning of my simulation?
- (Xilinx Answer 38671) - Why does CORE Generator crash when I try to load my COE file?
- (Xilinx Answer 45434) - Why is the frame_rst output signal not available in EDK, when using the pCore interface with Live mode input?
- (Xilinx Answer 45438) - Why does the Video Scaler fail to complete the processing of an output frame larger than 2048 x 2048?
- (Xilinx Answer 46438) - Why does the Video Scaler start producing outputs lines earlier than expected, when cropping feature of the Video Scaler?
- (Xilinx Answer 46488) - Why do I get a TCL error when trying to simulate the Video Scaler in an EDK Project?
- (Xilinx Answer 47523) - Why do the AXI4-Lite register readbacks fail sometimes in simulation?
Known Issues (ISE) - (Xilinx Answer 50708)-Why does the Video Scaler fail stream properly when using live mode?
- (Xilinx Answer 51232)-Why does my software hang when using the Video Scaler pCore driver in EDK?
- (Xilinx Answer 52285) - Why doesn't the INTC_IF interface pin intr_coef_mem_rdbk_rdy and the intr_coef_mem_rdbk_rdy register behave according to the documentation?
Known Issues (Vivado) - (Xilinx Answer 47452) - Why are my outputs always driven to zero when using Vivado Synthesis?
- (Xilinx Answer 50708) - Why does the Video Scaler fail stream properly when using live mode?
- (Xilinx Answer 51232) - Why does my software hang when using the Video Scaler pCore driver in EDK?
- (Xilinx Answer 52285) - Why doesn't the INTC_IF interface pin intr_coef_mem_rdbk_rdy and the intr_coef_mem_rdbk_rdy register behave according to the documentation?
- (Xilinx Answer 52289) - Why does writing to the Status Register fail to clear the Error bits?
LogiCORE IP Video Scaler v5.0 There is a v5.0 rev1 patch available in
(Xilinx Answer 45439).
This patch is intended to fix issues listed below as
(Xilinx Answer 45438),
(Xilinx Answer 46438),
(Xilinx Answer 46488) and
(Xilinx Answer 47523).
- Initial release in ISE Design Suite 13.3
Supported Devices - Virtex-7
- Virtex-7 XT (7vx485t)
- Virtex-7 -2L
- Kintex-7
- Kintex-7 -2
- Virtex-6 XC CXT/LXT/SXT/HXT
- Virtex-6 XQ LXT/SXT
- Virtex-6 -1L XC LXT/SXT
- Spartan-6 XC LX/LXT
- Spartan-6 XA
- Spartan-6 XQ LX/LXT
- Spartan-6 -1L XC LX
New Features - ISE 13.3 tools support
- Added AXI-Stream interfaces on I/O
Resolved Issues - (Xilinx Answer 41489) - Why does the Video Scaler always generate for 4 phases, when Constant mode is selected?
- (Xilinx Answer 42509) - What are the valid values for the aperture_start_pixel and the aperture_end_pixel?
- (Xilinx Answer 43079) - Why does the Video Scaler fail to complete the processing of an input frame larger than 2048 x 2048?
- (Xilinx Answer 43080) - Why is the Video Scaler constant mode GUI estimated frame rate slower than expected?
- (Xilinx Answer 43582) - Why are the last few lines of my output video frame missing when upscaling?
Known Issues - (Xilinx Answer 32127) - Why do I receive X_ARAMB36 Block RAM memory collisions when simulating the Video Scaler?
- (Xilinx Answer 37094) - Why does intr_output_error assert unexpectedly at the beginning of my simulation?
- (Xilinx Answer 38671) - Why does CORE Generator crash when I try to load my COE file?
- (Xilinx Answer 45434) - Why is the frame_rst output signal not available in EDK, when using the pCore interface with Live mode input?
- (Xilinx Answer 45438) - Why does the Video Scaler fail to complete the processing of an output frame larger than 2048 x 2048?
- (Xilinx Answer 46438) - Why does the Video Scaler start producing outputs lines earlier than expected, when cropping feature of the Video Scaler?
- (Xilinx Answer 46488) - Why do I get a TCL error when trying to simulate the Video Scaler in an EDK Project?
- (Xilinx Answer 47523) - Why do the AXI4-Lite register readbacks fail sometimes in simulation?
- (Xilinx Answer53540) -Why does writing the coeffients fail, when following the documenation for the write enable signal timing?
LogiCORE IP Video Scaler v4.0 There is a v4.0 rev3 patch available in
(Xilinx Answer 41488).
This patch is intended to fix issues listed below as
(Xilinx Answer 41489),
(Xilinx Answer 43079),
(Xilinx Answer 45438),
(Xilinx Answer 46438) and
(Xilinx Answer 46488).
- Release in ISE Design Suite 13.1
Supported Devices - Virtex-6 XC CXT/LXT/SXT/HXT
- Virtex-6 XQ LXT/SXT
- Virtex-6 -1L XC LXT/SXT
- Spartan-6 XC LX/LXT
- Spartan-6 XA
- Spartan-6 XQ LX/LXT
- Spartan-6 -1L XC LX
- Virtex-5 XC LX/LXT/SXT/TXT/FXT
- Virtex-5 XQ LX/ LXT/SXT/FXT
- Spartan-3A DSP
New Features - Added AXI Lite interface to pCore, removing the PLB interface.
- Added Coefficient readback facility.
Resolved Issues - Fixed dual-engine 4:2:0 support.
- (Xilinx Answer 40950) - Why is the Video Scaler so large when using the pCore interface?
- (Xilinx Answer 40203) - When using the constant interface, why do I see ghosting in the horizontal direction, when downscaling an image larger than 720p?
Known Issues - (Xilinx Answer 32127) - Why do I receive X_ARAMB36 Block RAM memory collisions when simulating the Video Scaler?
- (Xilinx Answer 37094) - Why does intr_output_error assert unexpectedly at the beginning of my simulation?
- (Xilinx Answer 38671) - Why does CORE Generator crash when I try to load my COE file?
- (Xilinx Answer 41489) - Why does the Video Scaler always generate for 4 phases, when Constant mode is selected?
- (Xilinx Answer 42509) - What are the valid values for the aperture_start_pixel and the aperture_end_pixel?
- (Xilinx Answer 43079) - Why does the Video Scaler fail to complete the processing of an input frame larger than 2048 x 2048?
- (Xilinx Answer 43080) - Why is the Video Scaler constant mode GUI estimated frame rate slower than expected?
- (Xilinx Answer 43582) - Why are the last few lines of my output video frame missing when upscaling?
- (Xilinx Answer 45434) - Why is the frame_rst output signal not available in EDK, when using the pCore interface with Live mode input?
- (Xilinx Answer 45438) - Why does the Video Scaler fail to complete the processing of an output frame larger than 2048 x 2048?
- (Xilinx Answer 46438) - Why does the Video Scaler start producing outputs lines earlier than expected, when cropping feature of the Video Scaler?
- (Xilinx Answer 46488) - Why do I get a TCL error when trying to simulate the Video Scaler in an EDK Project?
LogiCORE IP Video Scaler v3.0 There is a v3.0 patch available in
(Xilinx Answer 37799).
Rev1 of this patch is intended to fix issues listed below as
(Xilinx Answer 40950).
Rev2 of this patch is intended to fix issues listed below as
(Xilinx Answer 41489).
- Release in ISE Design Suite 12.3
New Features - RGB/4:4:4 compatibility (previously YC 4:2:2 and YC4:2:0 only)
- 8, 10 and 12-bit compatibility (previously 8 bits only)
- Selection of single, dual or triple-engine implementations to increase throughput if required (previously only single-engine available)
- Spatial resolution up to 4096x4096 (previously up to 1920x1080)
- Shareable coefficients
- Full EDK GUI in addition to existing CORE Generator GUI (previously, EDK GUI was very rudimentary)
- Pre-loadable coefficients in Constant, GPP and EDK pCore modes (previously only in Constant mode)
- Core Version register added
- Sharper Upscaling coefficients in xscaler_coefs.c file for the pCore interface
Resolved Issues - CR 534850 - Reversed order of coefficients in .coe file, to match the GPP interface
Known Issues - Selection of Virtex-6 device, specifically the -3 speed-grade, causes the CORE Generator tool to error out
- Video corruption in YC4:2:0
- (Xilinx Answer 32127) - Why do I receive X_ARAMB36 block RAM memory collisions when simulating the Video Scaler?
- (Xilinx Answer 40950) - Why is the Video Scaler so large when using the pCore interface?
- (Xilinx Answer 37094) - Why does intr_output_error assert unexpectedly at the beginning of my simulation?
- (Xilinx Answer 38671) - Why does the CORE Generator tool crash when I try to load my COE file?
- (Xilinx Answer 40203) - When using the constant interface, why do I see ghosting in the horizontal direction, when downscaling an image larger than 720p?
- (Xilinx Answer 41489) - Why does the Video Scaler always generate for four phases when Constant mode is selected?
- (Xilinx Answer 42509) - What are the valid values for the aperture_start_pixel and the aperture_end_pixel?
- (Xilinx Answer 43582) - Why are the last few lines of my output video frame missing when upscaling?
- (Xilinx Answer 45434) - Why is the frame_rst output signal not available in EDK, when using the pCore interface with Live mode input?
- (Xilinx Answer 46438) - Why does the Video Scaler start producing outputs lines earlier than expected, when cropping feature of the Video Scaler?
LogiCORE IP Video Scaler v2.1 - Initial release in ISE Design Suite 12.1
New Features - (Xilinx Answer 33948) - Why is the frame_rstG (ScalerVReset) fixed at 21, which does not allow it to work for NSTC inputs?
Resolved Issues - (Xilinx Answer 33791) - Why does the Video Scaler pCore stop working after about 4-8 hours of operation?
- (Xilinx Answer 33790) - Why do I receive an XST Compiler:410 error when I target a Virtex-6 or Spartan-6 device using the pCore interface?
- (Xilinx Answer 33868) - Why do I not see any output when using the Video Scaler with a Memory Data Source and an Aperture Start Line of zero "0"?
- (Xilinx Answer 34202) - Why are the results wrong when using a core clock greater than 2x the input clock rate?
- (Xilinx Answer 33397) - Why does Constraint Interface limit my Aperture Start Pixel and Aperture End Pixel to 720p dimensions?
- (Xilinx Answer 34253) - Why does the Video Scaler Input FIFO appear to skip some lines?
- (Xilinx Answer 33398) - Why do I receive a warning about a missing top level when I generate the EDK Pcore interface?
- (Xilinx Answer 34479) - Why does my pCore not have the parameters that I selected in the CORE Generator software?
- (Xilinx Answer 34435) - How do input 4:2:0 chroma data when using a Memory Data Source?
- (Xilinx Answer 35382) - Virtex-6 and Spartan-6 core should not be used in production due to potential block RAM memory related problems
Known Issues - (Xilinx Answer 32127) - Why do I receive X_ARAMB36 block RAM memory collisions when simulating the Video Scaler?
- (Xilinx Answer 35638) - Why is the control register in big endian format, instead of little endian format as documented in the data sheet when targeting Spartan-6 or Virtex-6 devices?
- (Xilinx Answer 35460) - Why does frame_done not assert when I use the Video Scaler in 4:2:0 mode?
- (Xilinx Answer 37094) - Why does intr_output_error assert unexpectedly at the beginning of my simulation?
LogiCORE IP Video Scaler v2.0Important Note: This version of the Video Scaler should not be used to target Virtex-6 or Spartan-6 devices; see
(Xilinx Answer 35382). There was a v2.0 rev2 patch available in
(Xilinx Answer 33393). This patch was intended to fix issues listed below in
(Xilinx Answer 33790) and
(Xilinx Answer 33791).
- Initial release in ISE Design Suite 11.3
New Features - Support for Spartan-3A DSP-4 FPGA
- Support for Spartan-6 FPGA
- Support for Virtex-6 FPGA
- EDK pCore option can now be generated from the CORE Generator tool
- Constant (Fixed mode) option can now be generated from the CORE Generator software
- Video source can be either Live-feed or Memory-sourced
Resolved Issues - Timing closure now allows support for Spartan-3A DSP-4 FPGA
- (Xilinx Answer 32127) - Why do I have X_ARAMB36 block RAM memory collisions when simulating the Video Scaler v1.0?
Known Issues - (Xilinx Answer 33397) - Why does the Constraint Interface limit my Aperture Start Pixel and Aperture End Pixel to 720p dimensions?
- (Xilinx Answer 33398) - Why do I receive a warning about a missing top level when I generate the EDK Pcore interface?
- (Xilinx Answer 33790) - Why do I receive an XST Compiler:410 error when I target Virtex-6 or Spartan-6 devices using the pCore interface?
- (Xilinx Answer 33791) - Why does the Video Scaler pCore stop working after about 4-8 hours of operation?
- (Xilinx Answer 33868) - Why do I not see any output when using the Video Scaler with a Memory Data Source and an Aperture Start Line of zero (0)?
- (Xilinx Answer 33948) - Why is the frame_rst (ScalerVReset) fixed at 21, which does not allow it to work for NSTC inputs?
- (Xilinx Answer 34202) - Why are the results wrong when using a core clock greater than 2x the input clock rate?
- (Xilinx Answer 34253) - Why does the Video Scaler Input FIFO appear to skip some lines?
- (Xilinx Answer 34435) - How do I input 4:2:0 chroma data when using a Memory Data Source?
- (Xilinx Answer 34479) - Why does my pCore not have the parameters that I selected in the CORE Generator software?
- (Xilinx Answer 35460) - Why does frame_done not assert when I use the video scaler in 4:2:0 mode?
- (Xilinx Answer 37094) - Why does intr_output_error assert unexpectedly at the beginning of my simulation?
LogiCORE IP Video Scaler v1.0 - Initial release in ISE Design Suite 11.1
New Features
Resolved Issues
Known Issues - (Xilinx Answer 32127) - Why do I have X_ARAMB36 block RAM memory collisions when simulating the Video Scaler v1.0?
- (Xilinx Answer 33948) - Why is the frame_rst (ScalerVReset) fixed at 21, which does not allow it to work for NSTC inputs?
- (Xilinx Answer 34202) - Why are the results wrong when using a core clock greater than 2x the input clock rate?
- (Xilinx Answer 34253) - Why does the Video Scaler Input FIFO appear to skip some lines?
- (Xilinx Answer 37094) - Why does intr_output_error assert unexpectedly at the beginning of my simulation?