Serial RapidIO v5.1 - Virtex-II Pro Core fails timing when buffer is 32 words deep

AR#	31962	Search For Another Answer
Topic	RapidIO
Last Updated	04/08/2011
Status	Active

Description

During implementation of a Serial RapidIO Core for a Virtex-II Pro device, timing errors similar to the following might result:

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Timing constraint: TS_CLK0_BUF = PERIOD TIMEGRP "CLK0_BUF" 6.4 ns HIGH 50%
PRIORITY 0;

105562 paths analyzed, 13269 endpoints analyzed, 1 failing endpoint
1 timing error detected. (1 setup error, 0 hold errors)
Minimum period is 6.482ns.

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Slack: -0.082ns (requirement - (data path - clock path skew + uncertainty))
Source: rio_de_wrapper/buffer_sim/U0/buffer_top_inst/rx_buffer_inst/rx_bram_bank_inst/blk_mem_inst
/blk_mem_generator/valid.cstr/ramloop[7].ram.r/v2_noinit.ram/dp9x9.ram.B (RAM)
Destination: rio_de_wrapper/buffer_sim/U0/buffer_top_inst/rx_buffer_inst/log_buffer_empty (FF)

================================================================================

Timing constraint: TS_CLK0_BUF_TO_CLKDV_BUF = MAXDELAY FROM TIMEGRP "CLK0_BUF"
TO TIMEGRP "CLKDV_BUF" 6.4 ns;

92241 paths analyzed, 5789 endpoints analyzed, 1 failing endpoint
1 timing error detected. (1 setup error, 0 hold errors)
Maximum delay is 6.586ns.

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Slack: -0.186ns (requirement - (data path - clock path skew + uncertainty))
Source: rio_de_wrapper/buffer_sim/U0/buffer_top_inst/rx_buffer_inst/lnk_write_tag_5 (FF)
Destination: rio_de_wrapper/phy_wrapper/phy_4x_ser/U0/phy_4x_ser_gen.phy_ser/u_ollm_top/u_ollm_rx_top/o
llm_rx_userint/in_packet (FF)

Solution

The timing issues described above can occur in a Serial RapidIO v5.1 Core only when targeting a Virtex-II Pro device. The core is not supported in Virtex-II Pro if you select a "TX Buffer Depth" or "RX Buffer Depth" of 32 on page four of the core's customization GUI. The supported options are to select either 16 words or 8 words for the buffer depth.