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AR# 31963

10.1 EDK, MPMC v4.00.a - MPMC data sheet has incorrect MI_CONTROL settings

Description

Keywords: MI_CONTROL

When using the MPMC connected to a PPC440 through the MIB PIM, memory transactions do not work. Accesses through other PIMs, such as the PLB or XCL PIMs do work correctly. How do I resolve this issue?

Solution

The MI_CONTROL settings table in the MPMC data sheet contains incorrect values for the settings of the PPC440 MHS instance. Following is an updated table:

Memory Type...Memory Width...MI_CONTROL Burstwidth...Allowable MI_CONTROL Burstlengths
SDRAM.................................8.......................................32..........................................................4,8
SDRAM................................16......................................32..........................................................4,8
SDRAM................................32......................................32..........................................................4,8
SDRAM................................64......................................64.......................................................2,4,8
DDR/DDR2...........................8........................................32..........................................................4,8
DDR/DDR2...........................16......................................32..........................................................4,8
DDR/DDR2...........................32......................................64.......................................................2,4,8
DDR/DDR2...........................64......................................64..........................................................4,8

The updated table will be fixed starting with MPMC v5.00.a, to be released in EDK 11.1.
AR# 31963
Date Created 12/02/2008
Last Updated 12/07/2008
Status Active
Type General Article