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AR# 31987

Virtex-5 GTX/GTP RocketIO - Disparity Errors at near-end interface when using Far-end PCS Loopback.


The Virtex-5 RocketIO can use a Far-end Loopback mode to repeat back data it has received. In the parallel far-end loopback mode, clock correction is done prior to re-sending the data. This AR discusses potential disparity issues that can arise in this case.


When in Far-end Loopback mode, the GTP and GTX transceivers will retransmit the data they have received with matching disparity as required by PCI-Express. As a consequence, protocols that do not use a neutral disparity clock correction sequence will detect disparity errors on the looped back data.

This is a problem only with Clock Correction sequences since they can potentially be added or removed from the data stream. When a non-neutral character is removed and the data forwarded, the subsequent character will appear to have the incorrect disparity.

AR# 31987
Date Created 12/16/2008
Last Updated 02/18/2013
Status Active
Type General Article