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AR# 31993

LogiCORE Ram Based Shift Register v9.0 - I cannot build a Ram Based Shift Register less than 4 bits wide (depth of less than 16). Why?

Description

I cannot build a Ram Based Shift Register less than 4 bits wide (depth of less than 16). Why?

Solution

This is a limitation of the v8.0 and v9.0 Core. If you need a Shift Register with an address less than 4 bits wide, it is recommended that you build it using the HDL examples provided in the ISE Language Templates.

AR# 31993
Date Created 12/12/2008
Last Updated 05/21/2014
Status Archive
Type General Article