AR #31996 - LogiCORE FIR Compiler v4.0 - When the "Generate chan_in value in advance" parameter is used, why is the chan_in output delayed by the specified number of cycles, rather than being output early by the specified number of cycles?

AR#	31996
Part	IP-DSP Horizontal
Last Modified	2009-07-16 00:00:00.0
Status	Active
Keywords	channel, input, delay, channel, output, cycle, delay, offset

Solution

This applies to the post implementation timing simulation.

In FIR Compiler v5.0 and beyond, this issue is resolved, but it might appear that there is still a problem in some simulators. To work around this in those versions, you can simply shift the clock by 1/4 or 1/2 of the clock cycle.

In the FIR Compiler v4.0, this is due to a problem in the implementation of this feature; the counter that controls the delay is being initialized to the wrong value.

To work around this issue, set the "Generate chan_in value in advance" parameter to the difference between the number of channels and the desired delay (# of channels - # of cycle delay).

That is, if you have a 15-channel filter and want the delay to be 5 cycles, you would set the "Generate chan_in value in advance" parameter to 10 (15 channels - 5 cycle delay = 10).