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Serial RapidIO v5.1 - Buffer layer may corrupt single-cycle RX packets

AR# 32063

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Topic RapidIO
Last Updated 04/08/2011
Status Active
Description

Under specific circumstances, the RX buffer layer provided with the Serial RapidIO v5.1 core may corrupt single-cycle packets. An example of a single-cycle packet could be a DOORBELL response. 

The issue can occur when the RX buffer is close to empty, and the single-cycle packet enters the buffer from the PHY 2 clock cycles after the previous packet. The result is the single-cycle packet appears on the RX buffer output (toward the LOG layer) as corrupted or as a portion of a previous unrelated packet.

Solution


This issue will be fixed in the next core release. In the meantime, you can work around this issue by de-selecting the "Unified Clock" option on page 4 of the core's customization GUI. 

If your design must use the "Unified Clock" option, please open a WebCase and refer to this Answer Record: 
http://www.xilinx.com/support/clearexpress/websupport.htm


Revision History 

01/21/2009 - Initial Release
 
 
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