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AR# 32076

11.1 EDK - The FIFO Generator models in the XilinxCoreLib use different type declarations for the C_PRIM_FIFO_TYPE parameter between the VHDL version and the Verilog version


Keywords: fifo_generator_v4_2, fifo_generator_v4_3, ncsim

Verilog and VHDL FIFO Generator Models in XilinxCoreLib have different type declarations for C_PRIM_FIFO_TYPE.

This applies to both fifo_generator_v4_2 and fifo_generator_v4_3.
The VHDL model in XilinxCoreLib has the C_PRIM_FIFO_TYPE declared as a string. The Verilog model has it as an integer. This causes simulation failures if the user is switching between Verilog and VHDL as library source for the models. In the specific case observed, a VHDL source file instantiated the VHDL version of the fifo_generator_4_2 and assigned the C_PRIM_FIFO_TYPE a string value. This works as long as VHDL version of sim model used. If switched to Verilog models of XilinxCoreLib, users encounter the type mismatch error on the fifo_generator_4_2 instance.

Error occurs during elaboration phase with NCsim.
Error message:

ncelab: *F,GENPAR: VHDL generic FIFO_GENERATOR_Virtex-4_2.C_PRIM_FIFO_TYPE (/proj/gsd/edk/EDK_10.1_sp3/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/coregen_comp_defs.vhd: line 162, position 19) and verilog parameter being overridden FIFO_GENERATOR_Virtex-4_2.C_PRIM_FIFO_TYPE (/home/graces/NCsim_lib/XilinxCoreLib_ver/XilinxCoreLib_ver_source.v: line 3456, position 28) are not type compatible.

In coregen_comp_defs.vhd:
C_PRIM_FIFO_TYPE : string := "4kx4";
In XilinxCoreLib_ver_source.v:
parameter C_PRIM_FIFO_TYPE = 512;


There is no fix for the 4.3 FIFO generator (fifo_generator_v4_3.). However, this issue has been fixed in version 5.1 and is available in EDK 11.1.

The EDK 11.1 will be available at: http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp

AR# 32076
Date 04/16/2009
Status Active
Type General Article
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