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AR# 32090

MIG v3.0 - Release Notes and Known Issues for ISE 11.1 Update


This Release Notes and Known Issues Answer Record is for the Memory Interface Generator (MIG) v3.0 released in ISE 11.1 and contains the following information:  


- General Information  

- Software Requirements 

- New Features  

- Resolved Issues 

- Known Issues  


For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at: 



General Information  

MIG v3.0 is available through the ISE 11.1 Update. For a list of supported memory interfaces and frequencies, see the MIG User Guide: 



Software Requirements 

- Xilinx ISE Design Suite 11.1 

- Synplify Pro 9.6.2 support 

- 32-bit Windows XP 

- 32-bit Linux Red Hat Enterprise 4.0 

- 64-bit/32-bit Linux Red Hat Enterprise 4.0 

- 64-bit XP professional 

- 32-bit Vista business 

- 64-bit SUSE 10 

- 64-bit/32-bit Linux Red Hat Enterprise 5.0 support 

- 64-bit Windows Vista support 

- 32-bit SUSE 10 support 



New Features 

- Xilinx ISE Design Suite 11.1 software support 

- Removed DIRT strings and associated RLOC_ORIGIN constraints from the Virtex-5 DDR2 SDRAM UCF file. ISE 11.1 properly places and routes this logic without the DIRT Strings and RLOC_ORIGIN constraints. See the MIG User Guide for full details. 

- Replaced IDELAYCTRL constraints with the new IODELAY_GROUP constraints for Virtex-5 designs. 

- Replaced usage of DCMs with PLLs in Virtex-5 designs. Replaced GUI "Use DCM" option with "Use PLL" option. 

- Verify UCF and Update Design support for Virtex-5 Multi-Controller designs. 

- Verify UCF and Update Design support various UCF syntaxes and are now case insensitive. 

- Enhanced Controller Options page in the GUI. 

- Divided FPGA Options page for Virtex-5 designs into two pages ("FPGA Options" and "Extended FPGA Options"). 

- Removed "Preset Configurations" option from the GUI. 

- Removed unchangeable Mode Register settings from the GUI and combined the changeable Mode Registers settings into a single GUI page ("Memory Options"). 

- MIG GUI closes after clicking "Generate" ("Finish" page has been removed). 

- Added "Class for Data" option to Spartan-3 Generation designs. 

- Added ability to set WASSO limits for Spartan-3 Generation designs. 

- MIG output is compatible with CORE Generator's new directory structure. 

- DCI is now applied with respect to the group enabled for DCI (i.e., DQ/DQS or Address/Control), rather than according to the I/O direction of the signal. As a result, DM is now grouped with DQ/DQS, rather than Address/Control (as in previous releases). 

- Reduced the delay in selecting banks on the Bank Selection page for Multi-Controller designs. 


Resolved Issues 

DDR2 SDRAM Virtex-5  

- (Xilinx Answer 31802) MIG v2.3 - Virtex-5 DDR2 Multi-Controller: Example_Design and User_Design pin-outs do not match 

-- CR 478869 

- (Xilinx Answer 31771) MIG v2.3 - Virtex-5 DDR2 SDRAM Dual Rank - "ERROR: tRFC maximum violation during No Op occur in simulation" 

-- CR 481246 

- (Xilinx Answer 32004) MIG v2.3, Virtex-5 DDR2 - Incorrect directed routing constraints for Virtex-5 TXT devices when center column banks are used 

- Multi controller simulations work with x16 Qimonda memory parts. 

-- CR 498877 

- Added synthesis constraint "syn_preserve=1" for dm_ce primitive. 

-- CR 494895 

- "IOB=TRUE" attribute is replaced with new "IOB=FORCE" attribute. 

-- CR 482871 

- Resolved an issue with the Bank Management logic to properly replicate bank_valid_r. 

-- CR 469871 


DDR SDRAM Virtex-5  

- (Xilinx Answer 31588) MIG v2.3 Virtex-5 DDR SDRAM - Simulation will remain in reset if the value of the parameter RST_ACT_LOW is changed from "1" to "0" in the simulation test bench (sim_tb_top.v/.vhd) 

- CR 481244 

- "IOB=TRUE" attribute is replaced with new "IOB=FORCE" attribute. 

-- CR 482871 


QDRII SRAM Virtex-5  

- (Xilinx Answer 31580) MIG v2.3 Virtex-5 QDRII, DDRII, Multi-Controller - Provided active high reset logic does not work properly in simulation 

- Resolved issues within the phy_en .v/.vhd module to start the stage3 calibration using the appropriate srl_count value. This issue, in previous MIG versions, could cause the data between the two CQ bytes to not match after second stage calibration. 

- CR 504310 

- Command signals do not toggle after reset is de-asserted. 

-- CR 498610 

- "IOB=TRUE" attribute is replaced with new "IOB=FORCE" attribute. 

-- CR 482871 


DDRII SRAM Virtex-5  

- (Xilinx Answer 31580) MIG v2.3 Virtex-5 QDRII, DDRII, Multi-Controller - Provided active high reset logic does not work properly in simulation 


DDR2 SDRAM Virtex-4 Direct Clocking 

- (Xilinx Answer 31797) MIG v2.3 Virtex-4 DDR/DDR2 Direct Clocking - Extra IDELAYCTRL instance LOC causing WARNING:Place:851  

-- CR 480208 

- "IOB=TRUE" attribute is replaced with new "IOB=FORCE" attribute. 

-- CR 482871 

- Tri-state enable signal is turned on a half clock cycle earlier. 

-- CR 457315 


DDR2 SDRAM Virtex-4 Serdes Clocking  

- "IOB=TRUE" attribute is replaced with new "IOB=FORCE" attribute. 

-- CR 482871 

- Deleted the parameters Tbit_straddle and Tbit_straddle_1 from the read_data_timing spreadsheet. 

-- CR 481259 

- Added "IOB = FORCE" constraints in VHDL code for address, command and data tri-state. 

-- CR 505255 


DDR SDRAM Virtex-4  

- (Xilinx Answer 31797) MIG v2.3 Virtex-4 DDR/DDR2 Direct Clocking - Extra IDELAYCTRL instance LOC causing WARNING:Place:851  

-- CR 480208 

- "IOB=TRUE" attribute is replaced with new "IOB=FORCE" attribute. 

-- CR 482871 


QDRII SRAM Virtex-4  

- Command signals do not toggle after reset is de-asserted. 

-- CR 498610 

- "IOB=TRUE" attribute is replaced with new "IOB=FORCE" attribute. 

-- CR 482871 


DDRII SRAM Virtex-4  

- Command signals do not toggle after reset is de-asserted. 

-- CR 498610 

- "IOB=TRUE" attribute is replaced with new "IOB=FORCE" attribute. 

-- CR 48287 


DDR/DDR2 SDRAM Spartan-3  

- (Xilinx Answer 31801) MIG v2.3 Spartan-3A Starter Kit - When running the ISE project output by create_ise.bat, Translate fails with ERROR:ConstraintSystem:59  

-- CR 478919 

- (Xilinx Answer 31591) MIG v2.3 Spartan-3 Generation DDR/DDR2 SDRAM - Incorrect hierarchy for the fifo_we_clk constraint in the provided user_design UCF  

-- CR 480929 

- (Xilinx Answer 31734) MIG v2.3 Spartan-3 Generation DDR2 SDRAM - tRAS and tRFC specifications are violated for certain memory parts  

-- CR 484933 

- Corrected the UCF RLOC_ORIGIN constraints for xc3s1400a-ft256 device when top bank is selected for System Clock. 

-- CR 504837 

- Corrected the cal_ctl AREA_GROUP range in UCF file for devices xc3s50a-ft256 and xc3s50an-ftg256 when X4 memory part is selected for bank3. 

-- CR 504836 

- "IOB=TRUE" attribute is replaced with new "IOB=FORCE" attribute. 

-- CR 482871 

- Proper bit width is assigned to row_address1 in the addr_gen module. 

-- CR 479364 

- The example_design (synthesizable testbench) now toggles all data bits, expanding the testing coverage. 

-- 478022 

- Added UCF constraints for TS_CLK90 to TS_DQS_CLK for Spartan-3 Generation designs. 

-- CR 480282 


Updates to MIG User Guide  

- Added more information on QDR2 PCB guidelines to Appendix section. 

-- CR 499760  

-- CR 504682  

- Added clarification on trace matching requirements to Memory Implementation Guidelines of Appendix A. 

-- CR 491957  

- Added separate pin assignment rules in Appendix A for Virtex-4 and Virtex-5 QDRII designs. 

-- CR 496617  

- Appendix A section modified that Loop back signal is required only for Spartan designs. 

-- CR 491299  

- Added separate section "MIG integration in ISE" in Chapter 1. 

-- CR 473932  

- Moved information from simulation_help document to the MIG User Guide. 

-- CR 496413  

- Removed support for 72-bit DIMMs from Table 8-17 for Spartan-3A DSP FPGAs. 

-- CR 497709  

- Removed comments noting the XIL_ROUTE_ENABLE_DATA_CAPTURE environment variable. This is no longer required. 

-- CR 490624  

- Added notes as to why it is not required to use the signals auto_ref_req and refresh_done signals for Spartan-3 designs in the example_design test bench module. 

-- CR 493312  

- Information from (Xilinx Answer 31107) is moved to MIG user guide. 

-- CR 493211  

- Provided information on how to change the FIFO threshold values. 

-- CR 470112  

- Updated the Write and Read command sequence that the controller follows with respect to the FIFO status signals in "Limitations" section of Virtex-4 QDRII SRAM designs. 

-- CR 490757  

- Added description about write data pattern, address locations and the number of bursts used in synthesizable test bench for every design. 

-- CR 478024  

- Added description about driving unused bits from user interface. 

-- CR 477483  

- Added more description on user interface clocks. 

-- CR 499126  

- Added reference to clocking scheme section in User interface clocks section for details. 

-- CR 492683  

- Virtex-5 ODT description chapter has references to "Capturing the Last Data of Read Burst" section in XAPP858. 

-- CR 496238  

- Added detailed description on ODT0, ODT1 and CS0, CS1 for dual-rank DIMMs. 

-- CR 491649  

- Removed Dual-Rank DIMM from unsupported features list of Virtex-5 DDR2 SDRAM. 

-- CR 491434  

- Updated the "Required UCF and HDL Modifications for Pinout Changes" section. 

-- CR 476819  

- Added description of chip select bit within the af_addr bus for Virtex-5 DDR2 SDRAM design. 

-- CR 476818  


MIG Tool  

- (Xilinx Answer 31606) MIG v2.3, Virtex-5 DDR2 - Are CLK and CLK90 related?  

-- CR 481527 

- (Xilinx Answer 31772) MIG v2.3 - Known Issues for Verify UCF with Spartan-3 Generation devices 

-- CR 506103 

-- CR 480930 

-- CR 480928 

-- CR 480927 

- (Xilinx Answer 31590) MIG v2.3 - Memory parts created using the Create Custom Part feature are not visible in the GUI after relaunching MIG 

-- CR 459684 

-- CR 487931 

- (Xilinx Answer 31807) MIG v2.3 - Why does MIG crash after uploading my mig.prj and UCF to the "Update Design" tool?  

-- CR 478340 

-- CR 491681 

- (Xilinx Answer 31578) MIG v2.3 DDR2 SDRAM - Simulating with Qimonda models causes "Memory Allocation Failure" error 

-- CR 481248 

- Output drive strength option is enabled for the following DDR2 SDRAM memory parts - MT47H64M8XX-3, MT47H64M8XX-5E, MT47H64M8XX-25E-IT, MT8HTF6464AY-667 

-- CR 504835 

- Renamed Sheet1 and Sheet2 of Read_data_timing.xls in docs folder of MIG output to IODELAY_HIGH_Mode and 

IODELAY_NORMAL_Mode for Virtex-5 designs. 

-- CR 503008 

- Corrected the CLK_WIDTH value for the following DDR2 SDRAM memory parts. 

MT9HTF12872CHY-53E, MT9HTF12872CHY-667, MT16HTF25664HY-40E, MT16HTF25664HY-53E, MT16HTF25664HY-667. 

-- CR 502733 

- Virtex-4 SERDES DDR2 SODIMM/UDIMM frequency support is reduced to a max of 267MHz. 

-- CR 501550 

- MIG compares speed grade and package for Compatible FPGAs. 

-- CR 500794 

- Corrected the Max data width for XC3S5000FG676 device. 

-- CR 499253 

- Resolved the Verify UCF false warning message on rst_dqs_div signal for Spartan designs. 

-- CR 498903 

- MIG searches for the Custom Memory part in both output directory path and mig.prj path. 

-- CR 493688 

- MIG generates valid project file mig.prj in batch mode for already generated design with same component name and output folder. 

-- CR 493686 

- Fixed instantiation template issue for .vho files. 

-- CR 493054 

-- CR 481247 

- After clicking "Generate," MIG will close and not point to the path "tmp/_cg". 

-- CR 491529 

- For PPC440 designs, DDR2_RESET_N signal is allocated under Address group. 

-- CR 491079 

- Changed the group name of the "Address" to "Address/Control" on Bank selection screen. 

-- CR 490909 

- Corrected the X_CORE_INFO attribute tag name for Virtex-4 and Virtex-5 DDR SDRAM designs. 

-- CR 488618 

- Fixed unexpected configuration warning messages in Bank Selection page of MIG GUI for Spartan-3 Generation designs. 

-- CR 483278 

- Reduced Drive Strength is supported for DDR SDRAM and DDR2 SDRAM memories from MIG GUI. 

-- CR 482795 

- Fixed an issue when using the synthesis option "optimize_primitives" with Virtex-5 multiple interface designs. 

-- CR 481356 

- Resolved the pin allocation issues related to VRP/VRN for Virtex-5 Multi-Controller and multiple interface designs. 

-- CR 481353 

- MIG outputs Xilinx reference board files in "Component Name" directory. 

-- CR 478102 

- create_ise.bat file includes separate comment delimiters for Linux and Windows versions. 

-- CR 475066 

- MIG removes previously implemented files from PAR folder when ise_flow.bat is executed.  

-- CR 474031 

- Pin allocation algorithm is improved to reduce the pin allocation time for multi controller designs. 

-- CR 469244 

- Resolved issues with having to click options twice in GUI. 

-- CR 459772 

- When a MIG design is generated from Coregen within ISE, ISE will not overwrite the xmdf.tcl file when ISE is closed. 

-- CR 457612 

- New memory parts created using "Create Custom Part" are stored in project path area. 

-- CR 448842 

- MIG designs created with a Custom Part using the MT47H16M16XX-37E as the base part now properly pass all timing parameters during functional simulation 

-- 510254 

- MIG properly sets the CLK_WIDTH for MT16HTF25664HY devices 

-- 507100 

- MIG properly verifies Spartan-3 DDR/DDR2 designs against the +5/-6 tile rule. This verifies DQ bits are placed within 5 tiles above or 6 tiles below the associated DQS bit placement. 

-- 506013 


Known Issues  

(Xilinx Answer 31579) MIG v2.3, v3.0 Virtex-5 QDRII - "ERROR:Place:899 - The following IOBs use DCI and have been locked to the I/O bank #" 

(Xilinx Answer 32318) MIG v3.0, Virtex-5 QDRII - Design does not complete calibration in hardware when using Synplify Pro 9.6.2 as the synthesis tool 

(Xilinx Answer 32319) MIG v3.0 - A ".ise" project is not successfully created after I run the create_ise.bat file 

(Xilinx Answer 32320) MIG 3.0 - Issues can occur when generating/regenerating a MIG project with the same component name 

(Xilinx Answer 32375) MIG 2.3, 3.0, Virtex-5 QDRII - Potential for small margin between the CQ and FPGA clock after stage 2 calibration for frequencies between 125 - 250 MHz 

(Xilinx Answer 32475) MIG v3.0, Spartan-3 Generation DDR/DDR2 - Known issues with Verify UCF and Update Design 

(Xilinx Answer 32449) MIG v2.3, v3.0 Spartan-3 Generation DDR/DDR2 - Complete Pin Allocation Rules

AR# 32090
Date Created 04/09/2009
Last Updated 10/14/2014
Status Active
Type General Article
  • ISE Design Suite - 11.1