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AR# 32091

Endpoint Block Plus Wrapper v1.11 for PCI Express - Downstream Port model drops completions with length 64 bytes and greater


Known Issue: v1.11, v1.10.1, v1.10, v1.9, v1.8, v1.7, v1.6, v1.7, v1.6, v1.5, v1.4, v1.3, v1.2, v1.1

In a x4 or x8 core simulation using the Downstream Port (DSPORT) model, a completion with length of 64 bytes or greater (in the Byte Count field) returned to the DSPORT does not come through to the TRN_RD port of the DSPORT.


This is a known issue with the Downstream Port simulation model. The issue does not affect the functionality of the Endpoint core itself.

To work around the issue, a modification to the DSPORT simulation model is required. The simulation model file requiring changes is named "pci_exp_4_lane_64b_dsport.v" for Verilog simulations, or "pci_exp_4_lane_64b_dsport.vhd" for VHDL simulations.

For Verilog, change the code beginning on line 155205 as follows (note the original line is commented below):

LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_hotplug12_0_0_0 (
// .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_hotplug12_0_0_0_0_5222),

For VHDL, change the code beginning on line 191038 as follows (note the original line is commented below):

com_tlm_u_tlm_rx_data_snk_next_cur_drop_2 : LUT4
generic map(
INIT => X"0100"
port map (
-- I0 => com_tlm_u_tlm_rx_data_snk_cur_hp_msg_detect,
I0 => '0',
I1 => com_tlm_u_tlm_rx_data_snk_cur_pm_msg_detect,
I2 => com_tlm_u_tlm_rx_data_snk_tlp_uc,
I3 => com_tlm_u_tlm_rx_data_snk_un1_eof_q_2_1_5106,
O => com_tlm_u_tlm_rx_data_snk_N_10772

Revision History

06/24/2009 - Updated for ISE 11.2 and core version v1.11.
04/13/2009- Updated for ISE 11.1 and core version v1.10.
02/03/2009 - Initial Release.
AR# 32091
Date Created 02/03/2009
Last Updated 12/15/2012
Status Active
Type General Article
  • Endpoint Block Plus Wrapper for PCI Express