AR #32121 - 11.2 System Generator for DSP - Why do I see mismatches in HDL simulation with the System Generator generated testbench when my design contains the DDS Compiler block using either the frequency synthesis or SIN/COS Lookup Table?
11.2 System Generator for DSP - Why do I see mismatches in HDL simulation with the System Generator generated testbench when my design contains the DDS Compiler block using either the frequency synthesis or SIN/COS Lookup Table?
| AR# | 32121 |
| Part | SW-SysGen |
| Last Modified | 2009-09-10 00:00:00.0 |
| Status | Active |
| Keywords | SysGen, sysgenDDC, mdl, ModelSim, sin, cos, LUT, lookup-table |
Description
Keywords: SysGen, sysgenDDC, mdl, ModelSim, sin, cos, LUT, lookup-table
Why do I see mismatches in HDL simulation with the System Generator generated testbench when my design contains the DDS Compiler block using either the frequency synthesis or SIN/COS Lookup Table?
Solution
This is because of a known issue with differences of how floating point results are handled between Xilinx System Generator for DSP and ModelSim. There should only be subtle differences in the lowest 1 or 2 LSBs of the DDS Compiler output and can be safely ignored.This issue is resolved in 11.3 with the latest version of the DDS Compiler v4.0.