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AR# 32122

Serial RapidIO v5.1 - Re-Transmit Suppression Support bit set incorrectly as 1'b0


The User Guide says that the Re-Transmit Suppression Support bit in the PHY CAR register (PHY Offset 0x10, bit 25) has a reset value of 1'b1, but when the register is read, the value comes back as 1'b0.


The Serial RapidIO core supports the Re-Transmit Suppression feature, but the bit is set incorrectly in the core's PHY Processing Element Features Capability Register. Both simulations and hardware implementations are affected. Because the bit is Read-only, it cannot be set with a Maintenance Write.

Note that the Re-Transmit Suppression Mask also does not reset to the value selected in CORE Generator (it resets to all 0's). The mask bits are R/W, so they can be overwritten to the desired values with a Maintenance Write.

These issues will be fixed in a future release of the core.

Revision History

02/12/2009 - Initial Release

AR# 32122
Date Created 02/12/2009
Last Updated 12/15/2012
Status Active
Type General Article