AR #32147 - ISE Design Suite 11 Known Issues

AR#	32147
Part	SW-Install
Last Modified	2009-09-09 00:00:00.0
Status	Active
Keywords	alert, readme, release, notes, Project Navigator, iMPACT, EDK, SDK, PlanAhead, DSP

Solution

For IP Known Issues, see:
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

Other Known Issues Answer Records

(Xilinx Answer 32288) 11.1 CORE Generator - Known Issues for CORE Generator 11.1
(Xilinx Answer 32420) 11.1 ChipScope Pro - Release Notes and Known Issues
(Xilinx Answer 32174) 11.1 System Generator for DSP - Release Notes, README, and Known Issues List
(Xilinx Answer 32176) 11.1 AccelDSP Synthesis Tool - Release Notes, README, and Known Issues List
(Xilinx Answer 32168) 11.1 EDK - EDK Master Answer Record List
(Xilinx Answer 32440) 11.1 iMPACT - Release Notes and Known Issues
(Xilinx Answer 32295) 11.1 ISE - Known Issues for Xilinx software licensing in ISE 11.1
(Xilinx Answer 32492) 11.1 ISE Design Suite Install - Known Issues for ISE Design Suite Install
(Xilinx Answer 33055) 11.2 ISE Design Suite - XilinxUpdate (11.2) Known Issues README
(Xilinx Answer 33381) ISE Design Suite 11 - ISE Simulator (ISim) Known Issues
(Xilinx Answer 32525) 11.1 PlanAhead Known Issues
(Xilinx Answer 32548) 11.1 ISE - Known Issues for Project Navigator 11.1
(Xilinx Answer 32511) 11.1 XST - Known issues

Current Known Issues

BitGen

(SP3) (Xilinx Answer 33223) 11 EDK - ERROR:PhysDesignRules:1690 - Incomplete PLL_ADV to PCC440 programming.
(SP3) (Xilinx Answer 33356) Spartan-6 FPGA MCB - X4 memory components are not supported until IDS 11.4 (MIG 3.3)
(SP3) (Xilinx Answer 33357) Spartan-6 FPGA MCB - Port 3 is not supported in read mode when all 6 ports are configured

Constraints Editor

(SP3) (Xilinx Answer 30506) 11.1 Known Issue - Timing Analyzer - Timing Analyzer fails to open Constraint Editor for a design with multiple UCF files
(SP3) (Xilinx Answer 32453) 11.1 Constraints Editor Known Issue - Docking or Floating causes errors in editing constraints
(SP3) (Xilinx Answer 32455) 11.1 Constraints Editor Known Issue - When I attempt to select my input clock in Constraints Editor, all I see is the clock that comes out of my ISERDES
(SP3) (Xilinx Answer 32483) 11.1 Known Issue - Constraints Editor - Why does my Net Period constraint show "NA" for my clock
(SP3) (Xilinx Answer 32838) 11.1 Constraints Editor - Non-Clock nets are listed for Spartan-6 design

MAP

(SP3) (Xilinx Answer 31620) 10.1 Virtex-5 MAP - ERROR:PhysDesignRules:1242 - Invalid connection used for ILOGIC
(SP3) (Xilinx Answer 31788) 11.x ChipScope Pro - "ERROR:MapLib:990 - Map has detected that you are using ChipScope Pro cores generated prior to version 10.1..."
(SP3) (Xilinx Answer 31827) 10.1 MAP - MAP fails with error: "DeleteInterpProc called with active evals" during Phase 10.29
(SP3) (Xilinx Answer 33340) 11.2 MAP/PAR - What is meant by Multi-Threading support in ISE 11.2?

PAR

(SP3) (Xilinx Answer 32388) 10.1 ChipScope CORE Generator - ERROR:PhysDesignRules:10 / WARNING:PhysDesignRules:10 - The network <CONTROL<2>> is completely unrouted.
(SP3) (Xilinx Answer 32544) Embedded Tri-mode Ethernet MAC Wrapper (Virtex-4) v4.7 - Implementation of MII interface might fail in MAP due to I/O banking rules
(SP3) (Xilinx Answer 32632) SPI-4.2 v9.1- "ERROR:Place:909 - Regional Clock Net "core_pl4_src_top0/tsclk_gp" cannot possibly be routed..." message during Map for Source core
(SP3) (Xilinx Answer 33021) 11.2 Virtex-6 Place - Designs with very low utilization may have very poor QOR
(SP3) (Xilinx Answer 33153) 11.2 Spartan-6 PAR - Incorrect WARNING:ParHelpers:79 message
(SP3) (Xilinx Answer 33212) 11.2 Virtex-5 PAR - Misleading Information in Pad Report when DCI Cascade feature is being used
(SP3) (Xilinx Answer 33362) Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper v1.3 - "Warning:Par:468 - Your design did not meet timing" seen in some configurations

Simulation Libraries

(SP3) (Xilinx Answer 12823) 10.1 PrimeTime/Timing Analysis - What Xilinx product families/devices are supported?
(SP3) (Xilinx Answer 31399) 10.1: UniSims, SimPrims- DCM simulation models do not work when the input clock has jitter
(SP3) (Xilinx Answer 33111) LogiCORE Ethernet Statistics v3.2 - Error regarding no matching objects found seen in the example design timing simulation

SmartXplorer

(SP3) (Xilinx Answer 32691) 11.1 SmartXplorer - Problems running SmartXplorer in command line mode
(SP3) (Xilinx Answer 33219) 11.2 Smartxplorer - ERROR "Could not determine cost table value from strategy name" while copying the best strategy

Timing

(SP3) (Xilinx Answer 30063) 11.1 Known Issue - Constraints Editor/Timing Analyzer - Wrong timing constraint is edited when "Editing Constraints" from Timing Analyzer
(SP3) (Xilinx Answer 31855) 11.1 Release Note - Timing - Why do I see Component Switching Limit values change in my timing report for PLLs and DCMs?
(SP3) (Xilinx Answer 32106) 10.1.3 TRCE - I am seeing an extremely large number of paths analyzed in my timing report
(SP3) (Xilinx Answer 32111) 11.1 Known Issue - Timing Analyzer/trce - Advanced Analysis neglects Component Switching Limits
(SP3) (Xilinx Answer 32120) 11.1 Release Notes - PAR/Timing Analyzer/trce - Why do I see Component Switching Limit warnings in my 11.1 PAR report?
(SP3) (Xilinx Answer 32123) 10.1i ISE - Project Navigator fails opening a 10.1i project: "FATAL_ERROR:Portability:PortDynamicLib.c:358:1.29"
(SP3) (Xilinx Answer 32325) 11.1 Known Issue - Timing Analysis, Virtex-5 - Why does Timing Analyzer fail to issue a Max Period Warning when I use a CRC32 component?
(SP3) (Xilinx Answer 32441) 11.1 Known Issue - Timing - Discrete Jitter for PLL/DCM Clock Uncertainty is pessimistic
(SP3) (Xilinx Answer 32445) 11.1 Known Issue - Timing - Incorrect timing analysis associated with input clocks on BUFGMUX
(SP3) (Xilinx Answer 32457) 11.1 Timing Known Issue - OFFSET IN with FALLING keyword appears to be off by a whole clock cycle
(SP3) (Xilinx Answer 32458) 11.1 Timing Analyzer Release Note - How do you cross-probe to FPGA Editor from Timing Report?
(SP3) (Xilinx Answer 32505) 11.1 Timing Analyzer - Cross-probing with Timing Analyzer into FPGA Editor is causing warnings
(SP3) (Xilinx Answer 32527) 11.1 ISE - Are Asian characters allowed in the directory path for Project Navigator projects?
(SP3) (Xilinx Answer 32543) 11.1 Timing - Incorrect clock analysis after inverting my clock with a BUFIO2 or an INV
(SP3) (Xilinx Answer 32630) 11.1 Constraints - When I use the * wildcard, several of my PINs are missing from my TIMEGRP
(SP3) (Xilinx Answer 32793) 11.1 Constraints System - Period Constraint from HDL not propagating to PCF
(SP3) (Xilinx Answer 32845) 11.1 Timing Analyzer - The pin name does not match in the Query Nets report and FPGA Editor
(SP3) (Xilinx Answer 32953) 11.2 Timing Analysis - Not correctly using attribute CLKFX_MD_MAX in the Clock Uncertainty equation
(SP3) (Xilinx Answer 32954) 11.2 Timing - Derived clock report does not have clock name for Spartan-6 reference design
(SP3) (Xilinx Answer 32955) 11.2 Timing Analyzer - Clock skew calculations ignores the PRIORITY keyword on the PERIOD constraint
(SP3) (Xilinx Answer 32957) 11.2 Constraint System - Net PERIOD constraints are been pushed from the REFCLK input to the RXRECCLK output of GTP/GTX
(SP3) (Xilinx Answer 33007) 11.1 Timing, Virtex-4 - "WARNING:Timing:3327 - Timing Constraint" - Component Switching Limit is limited by DLL portion of the DCM when both DLL and DFS DCM outputs are used
(SP3) (Xilinx Answer 33019) Spartan-6 Clocking - DCM_CLKGEN Spread Spectrum Clock Generation feature support
(SP3) (Xilinx Answer 33113) 11.2 Timing Analyzer - Autogenerated constraints report incorrect value for clk to pad
(SP3) (Xilinx Answer 33354) 11.3 EDK - ML510 Timing error on NET "Ethernet_MAC/Ethernet_MAC/phy_tx_clk_i" MAXSKEW = 5 ns;
(SP3) (Xilinx Answer 33363) Virtex-6 Embedded Tri-mode Ethernet MAC Wrapper v1.3 - With 16-bit client interface, the wrong clock is used to analyze some client-side Ethernet MAC signals

Older Known Issues Resolved in 11.3

(SP2) (Xilinx Answer 32835) 11.1i - Constraints Editor - Period Constraint value not being updated after using validate constraint
(SP2) (Xilinx Answer 32836) 11.1i - Constraints Editor - Constraints Editor does not list all the top level clocks of the design
(SP2) (Xilinx Answer 32837) 11.1i - Constraints Editor - Clock port is to be seen while providing OFFSET IN constraints
(SP2) (Xilinx Answer 17454) 11.1 RTL Viewer - In the RTL view, an instantiated core does not appear to be connected
(SP2) (Xilinx Answer 14394) 11.1 Schematic - Non-English international characters are not accepted in schematic signal names or as text messages on a schematic
(SP2) (Xilinx Answer 30207) 11.1 Schematic Editor - Cannot change CValues attribute to the Constant Symbol
(SP2) (Xilinx Answer 32497) 11.1 ISE Text Editor - Control-Z (undo) fails to undo changes made by the Replace function
(SP2) (Xilinx Answer 32383) 11.1 Release Note - Timing Analyzer/PlanAhead - Timing parameter link opens data sheet, but "No matches were found."
(SP2) (Xilinx Answer 32442) 11.1 Known Issue - Timing Analyzer - Crossprobing from Queue Timegroups does not work
(SP2) (Xilinx Answer 32456) 11.1 Timing Known Issue - MAXSKEW constraint shows a violation, but the report says it met timing
(SP2) (Xilinx Answer 32460) 11.1 Timing Known Issue - "FATAL_ERROR:Timing:bastwoffsetpref.c:679:1.160.14.3.10.1 - Clock arrival time not found"
(SP2) (Xilinx Answer 32469) 11.1 Timing Known Issue - "INTERNAL_ERROR:XdmHelpers:Xdh_TimeWrapper.c:843:1.23"
(SP2) (Xilinx Answer 32470) 11.1 Known Issue - Timing Analyzer - Does not analyze paths through Virtex-5 block RAM
(SP2) (Xilinx Answer 32844) 11.1 Timing Analyzer - "Saving to report" message stays in the console after the saving is done
(SP1) (Xilinx Answer 32351) 11.1 Constraints System - "ERROR:NgdBuild:755 - "../../../.ncf" Line 27: Could not find net(s)"
(SP1) (Xilinx Answer 3470) 11.1 Constraints - How do I LOC a PAD to an edge, multiple sites, or banks?
(SP1) (Xilinx Answer 32518) 11.1 Virtex-5 MAP - OSERDES/IODELAY/OBUFDS using IOSTANDARD DIFF_HSTL_II_DCI not mapped correctly
(SP1) (Xilinx Answer 32519) 11.1 MAP - "INFO:Map:91" is unnecessarily alarming
(SP1) (Xilinx Answer 32520) 11.1 MAP - Crash while "Running related packing..."
(SP1) (Xilinx Answer 32521) 11.1 Virtex-5 MAP - Incorrect optimization of latch with Gate driven by constant "1", but GE driven by active signal
(SP1) (Xilinx Answer 32522) 11.1 Virtex-5 MAP - There is a discrepancy in block RAM utilization reporting between the overall MAP utilization report and the model level utilization report
(SP1) (Xilinx Answer 32523) 11.1 Virtex-5 MAP - Maximum net name length of 2048 characters exceeded by some Synplicty netlists
(SP1) (Xilinx Answer 32524) 11.1 Virtex-5 PACK - Unroutable carry chain connections
(SP1) (Xilinx Answer 32526) 11.1 Spartan-3A Place - Crash during Phase 4.2 of MAP or PAR
(SP1) (Xilinx Answer 32528) 11.1 Spartan-3A Place - Timing driven mapping fails with ERROR:Place:848
(SP1) (Xilinx Answer 32530) 11.1 Spartan-3A Place- Crash after Phase 4.2 dues to loadless clock buffer
(SP1) (Xilinx Answer 32531) 11.1 Virtex-5 Place - Clock Placer does not handle placement of BUFR driving BUFG properly
(SP1) (Xilinx Answer 32533) 11.1 Spartan-3A Router - Hold Time router not able to find solution that 10.1 router used
(SP1) (Xilinx Answer 32534) 11.1 Virtex-5 Route - Router creates route-through conflict
(SP1) (Xilinx Answer 32495) 11.1 ISE Text Editor - On Linux 64, a split screen displays different color coding for the two panes
(SP1) (Xilinx Answer 13920) 11.1 Timing Analyzer - My FROM:TO constraint picks up the wrong paths (TNM)
(SP1) (Xilinx Answer 19555) 11.1 Timing - Does Timing Analyzer provide phase shift information on external clocks generated by DCM?
(SP1) (Xilinx Answer 32461) 11.1 Timing - I see that I have setup violations, but the paths are not reported
(SP1) (Xilinx Answer 7221) 11.1 Timing - For a design with two clocks or period constraints in the BUFGMUX, which constraint has priority in the final analysis?