Xilinx has determined that the Clock Correction feature of the Virtex-5 GTX transceiver can cause data corruption on the Receiver when a clock correction sequence is skipped or added. For detailed information about the Clock Correction feature, see the Virtex-5 FPGA RocketIO GTX Transceiver User Guide (UG198).
This issue can occur when all the following conditions are true:
When the conditions described above are met, the Clock Correction feature of the Virtex-5 GTX transceiver must be disabled. This Answer Record discusses the potential work-arounds available.
If the application permits, implement one of the following options:
If these options are not viable due to layout or protocol limitations, the user application must implement the fabric clock correction module located at:
The steps required to instantiate this block and fabric utilization estimates are outlined in the Virtex-5 FPGA RocketIO GTX Transceiver Clock Correction Module (XTP037), located at:
For individual IP affected by this issue, please refer to the following Answer Records:
Other protocols which might experience this problem:
Q: Is Aurora affected by this issue?
A: No, Aurora uses a 2-byte CC sequence.
Q: Is the GTP affected by this issue?
A: No, the GTP uses a different clock correction circuit which does not exhibit this problem.
Q: Is the Virtex-6 GTX affected?
A: No, the GTX does not exhibit this failure.
Q: When will the affected IP be updated?
A: For individual Xilinx IP, please refer to the Answer Records above. The RocketIO Wizard will be updated to use the fabric work-around by 11.2 and will implement attribute changes to protocol templates where applicable.