Solution

For System Generator for DSP Release Notes from other versions, see (Xilinx Answer 29595).

Release Notes and Known Issues in System Generator for DSP 11.1

Please read the documentation, because it answers questions you might have about changes to the functionality or the look from previous versions of System Generator for DSP. The System Generator User Guide is accessible in PDF format at:
http://www.xilinx.com/ise/optional_prod/system_generator.htm

11.1 System Generator Enhancements
Linux Support
System Generator now supports the Red Hat Enterprise Linux 4 WS (32 and 64-bit) operating system. The topic Installing System Generator On the Linux OS provides detailed installation instructions that are specific to Linux.

New MATLAB 2008b Support
For this release, System Generator now supports MATLAB 2008b as well as MATLAB 2008a.

Using Platform Studio SDK with System Generator
The Xilinx Platform Studio Software Development Kit (SDK) is an Integrated Development Environment for creating software platform designs. The SDK is an eclipse-based IDE that makes it easier to write high quality C/C++ code for Xilinx embedded
processors. System Generator provides access to the SDK by automatically generating an SDK workspace and providing a 'hello world" program template that contains example code which allows users to write productive code in a short period of time. For more details on how this feature works, refer to the topic titled Using Platform Studio SDK.

Updated Design Examples
For this release, the designs in the Examples folder have been updated using the latest IP and targeting the latest devices.

FAQ

Installation and setup
- What software is required to install System Generator for DSP? See (Xilinx Answer 17966).
- How can I tell if the DSP Tools are installed and configured for use in MATLAB? See (Xilinx Answer 32257).
- How can I switch between multiple versions of System Generator for one MATLAB installation? See (Xilinx Answer 24842).
- How can I install just the DSP Tools without reinstalling all of the IDS tools? See (Xilinx Answer 32258).
- Which version of System Generator supports the latest version of MATLAB? See (Xilinx Answer 25306).
- Why do I receive "Error while executing C MEX S-function 'sysgen', (mdlTerminate). Unexpected unknown exception from MEX file" when I simulate my System Generator model? How do I set up my system environment properly? See (Xilinx Answer 31095).
- When using System Generator on Windows Vista, why do I receive the error: "gcc.exe: installation problem, cannot exec `cc1': No such file or directory. Error occurred during "Simulation Initialization"? See (Xilinx Answer 30977).
- When using System Generator on a 64-bit XP machine, why do I receive a message stating, "There is a problem with your Xilinx ISE installation or with your Xilinx environment variable" and "could not run java.exe"? See (Xilinx Answer 29512).

MATLAB and Simulink interaction
- Why do I receive an error message stating "continuous sample times are not allowed" when driving a Simulink Spectrum Scope with Xilinx System Generator blocks? See (Xilinx Answer 31933)
- Why do I receive a "xlSimulationRequired" or "Reference to a cleared variable sysgen_return_status" error when I try to generate the design? See (Xilinx Answer 21750).
- An indeterminate input data (also known as a NAN) error occurs when design is simulated. See (Xilinx Answer 23000).
- Why can't I access the quantization parameters in the FDATool in System Generator? See (Xilinx Answer 24616).
- Why do I receive a Simulink message stating, "Use of this data type requires a fixed-point license, but license checkout failed"? See (Xilinx Answer 25255).
- What is the recommended Simulink simulation solver? Why do I see incorrect behavior when a fixed-step solver is used? See (Xilinx Answer 23328).
- Why doesn't my data appear downsampled when I use "first value of frame" with a latency of 0 with the downsample block? (See Xilinx Answer 32810).

Third Party Synthesis Tools
- I cannot generate an NGC, Bitstream, Timing Analysis, or Hardware in the Loop target when using Synplify as my synthesis tool. Why? See (Xilinx Answer 24273).
- Why do I receive the message "Failed to execute command "project set {Synthesis Tool} {Synplify Pro (VHDL/Verilog)}"" when trying to use Synplify Pro for my synthesis tool from System Generator? See (Xilinx Answer 31112).
- Why are there simulation mismatches at the beginning of the HDL simulation generated from System Generator for DSP when Synplify is used for synthesis? See (Xilinx Answer 29170).

General
- How do I access the reload order information when using the FIR Compiler v4.0 in System Generator for DSP? See (Xilinx Answer 32344).
- Why do I see an instantiated register called "xlpersistentdff" in a System Generator for DSP design? See (Xilinx Answer 24257).
- JTAG Hardware Co-Sim with non-Xilinx parts in the chain causes error. See (Xilinx Answer 19599).
- Why do I receive a standard exception error message when I generate my model? See (Xilinx Answer 29430).

Known Issues
- Why does the design fail to generate when using a CORE Generator IP block or Multiple Sub-Systems in a design and the target path is more than 160 characters? See (Xilinx Answer 23614).
- Why do I receive the message "xledkpostgen>PLBPcoreBuilder at 234" when netlisting my EDK PCORE design from System Generator? See (Xilinx Answer 31068).
- Why is my reset signal on my FIFO not behaving the same in hardware as it did in software? See (Xilinx Answer 31294).
- When I use the CIC Compiler filter with an input data rate less than the system clock rate controlled by ND, I see mismatches between the simulation results in System Generator versus hardware co-simulation. See (Xilinx Answer 31455).
- When running a MATLAB Student Edition, why do I receive the error message "Error evaluating 'OpenFcn' callback of Xilinx Gateway In Block block (mask)"? See (Xilinx Answer 31934).
- Why do I receive "Fatal Internal Error" when my design contains "inport" and "output" blocks at the top level of my Simulink model for Data Import/Export? See (Xilinx Answer 31935).
- When running MAP, why do I receive "ERROR:Place:673 - DSP component is the start of a cascade of DSP components"? See (Xilinx Answer 31937).
- Why do I see mismatches in HDL simulation with the System Generator generated testbench when my design contains the DDS Compiler block using either the frequency synthesis or SIN/COS Lookup Table? See (Xilinx Answer 32121).
- When I load the PicoBlaze example, I receive a warning that it contains block(s) which have become outdated. See (Xilinx Answer 32187).
- Why am I unable to search the System Generator documentation and copy text from it when using MATLAB R2008a? See (Xilinx Answer 32172).
- The auto-generated testbench is unable to find the .dat files for ModelSim based simulation. See (Xilinx Answer 32312).
- When an internal error occurs during simulation of a System Generator model an internal error will continue to occur. See (Xilinx Answer 32313).
- Why do I receive an error when I try to simulate the demo design sysgenDDC? See (Xilinx Answer 32314).
- Designs with the EDK Processor block do not support automatic testbench generation or simulation compilation. See (Xilinx Answer 32331).
- Why do I receive NGDBuild:ERROR:604 in ISE Project Navigator after regenerating my System Generator project? See (Xilinx Answer 32339).

Linux Only
- Can I perform Ethernet-based hardware co-simulation on a Linux machine? See (Xilinx Answer 32221).
- Why is the System Generator blockset empty when I try to open it in Simulink when running on Linux? See (Xilinx Answer 32173).
- Why can't I generate a model to the same directory on Linux? See (Xilinx Answer 32315).