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AR# 32177

14.x Timing Closure - Use "Mapping Logic Onto Block RAM" to resolve timing issue caused by too many levels of logic


I have some unused Block RAMs. Can I use them to resolve the timing issue caused by having too many levels of logic?


XST can place some of the separate hierarchical modules into unused Block RAM. This function can help to resolve some specific timing issues. If your separate block has too many levels of logic andsatisfies the following criteria, you can attach a "Map Logic on BRAM (BRAM_MAP)" constraint to this block to let it pass the timing requirement.

- All outputs are registered.
- The block contains only one level of registers, which are output registers.
- All output registers have the same control signals.
- The output registers have a Synchronous Reset signal.
- The block does not contain multisources or tristate busses.
- Keep (KEEP) is not allowed on intermediate signals.

For more information about "Map Logic on BRAM (BRAM_MAP)", see the XST User Guide.

For additional suggestions and recommendations about timing closure, see the following Answer Records:

- Suggestions for avoiding high fanout signals, see (Xilinx Answer 9410)
- Suggestions for state machine optimization, see (Xilinx Answer 9411)
- Suggestions for long carry logic chains, see (Xilinx Answer 9412)
- Suggestions for I/Os 3-state enable paths, see (Xilinx Answer 9413)
- Suggestions for paths through TBUFs, see (Xilinx Answer 9414)
- Suggestions for timing through irrelevant paths such as RESET or ".SR" pin, see (Xilinx Answer 9415)
- Suggestions for using multi-cycle paths, such as a path through a ".CE" pin, see (Xilinx Answer 9416)
- Suggestions for avoiding too many levels of logic, see (Xilinx Answer 9417)
- Suggestions for timing constraints that miss their goals by 5% to 10%, see (Xilinx Answer 9418)
- Suggestions for timing constraints that miss their goals by 10% to 15%, see (Xilinx Answer 9419)

AR# 32177
Date Created 04/07/2009
Last Updated 12/15/2012
Status Active
Type General Article
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