Virtex-4/Virtex-5 Embedded Tri-mode Ethernet MAC Wrapper - 16-bit 1000BASE-X Verilog RX FIFO could incorrectly overflow

AR#	32186	Search For Another Answer
Topic	IP-DS-Embedded Tri-Mode EMAC
Last Updated	03/02/2009
Status	Active

Description

Keywords: 4.6, 1.5, full

The Verilog RX FIFO generate when using the 16-bit 1000BASE-X Client Interface option could incorrectly overflow resulting in a dropped frame. This is due to an incorrect range used to determine when the FIFO goes full. This does not effect the VHDL or Verilog 8-bit RX FIFO and does not effect the VHDL 16-bit RX FIFO. This problem exists in the Virtex-5 Embedded Tri-mode Ethernet MAC Wrapper v1.5 and earlier and in the Virtex-4 Embedded Tri-mode Ethernet MAC Wrapper v4.6 and earlier.

Solution

To work around this issue, change lines 843 to 852 of <core_name>/example_design/client/fifo/rx_client_fifo_16.v from:

always @(posedge wr_clk)
begin
if (wr_sreset == 1'b1)
wr_fifo_full <= 1'b0;
else if (wr_enable == 1'b1)
if (wr_addr_diff[10:3] == 8'b0 && wr_addr_diff[2:1] != 2'b0)
wr_fifo_full <= 1'b1;
else
wr_fifo_full <= 1'b0;
end

To:

always @(posedge wr_clk)
begin
if (wr_sreset == 1'b1)
wr_fifo_full <= 1'b0;
else if (wr_enable == 1'b1)
if (wr_addr_diff[10:4] == 7'b0 && wr_addr_diff[3:2] != 2'b0)
wr_fifo_full <= 1'b1;
else
wr_fifo_full <= 1'b0;
end

This issue is scheduled to be fixed in the next release of the Core Generator cores.