Serial RapidIO v5.1 - Core Example Design files infer latches in synthesis
Description
The VHDL version of the Serial RapidIO v5.1 core's example design produces latches in XST synthesis. Warnings similar to the following might occur for the reg_manager.vhd, tickler.vhd, and target_user.vhd sources:
"WARNING:Xst:737 - Found 1-bit latch for signal <mresp_data_26>. Latches may be generated from incomplete case or if statements."
In hardware, the result of these latches could exhibit as intermittently failing Maintenance writes or reads.
Solution
The latch issues described here will be fixed in the Serial RapidIO v5.2 core. In the meantime, the following changes can be made to the example design files to remove the latches:
In the "reg_manager.vhd" file:
Code from v5.1:
process (clk, reset_n) begin
if (reset_n = '0') then
mresp_data <= x"0000000000000000" after TCQ;
elsif (tx_cs = TX_GET_D0) then
mresp_data(0 to 31) <= mgt_rx_data after TCQ;
elsif (tx_cs = TX_GET_D1) then
mresp_data(32 to 63) <= mgt_rx_data after TCQ;
end if;
end process;
Change to this:
process (clk, reset_n) begin
if (reset_n = '0') then
mresp_data_int <= x"0000000000000000" after TCQ;
elsif rising_edge(clk) then
if (tx_cs = TX_GET_D0) then
mresp_data_int(0 to 31) <= mgt_rx_data after TCQ;
mresp_data_int(32 to 63) <= mresp_data_int2(32 to 63) after TCQ;
elsif (tx_cs = TX_GET_D1) then
mresp_data_int(0 to 31) <= mresp_data_int2(0 to 31) after TCQ;
mresp_data_int(32 to 63) <= mgt_rx_data after TCQ;
end if;
end if;
end process;
mresp_data <= mresp_data_int;
mresp_data_int2 <= mresp_data_int;
The Verilog example design (reg_manager.v) also requires modification:
Code from v5.1:
always @(sel_bus_q or mgt_di_phy or mgt_di_usr or mgt_di_log)
begin
case (sel_bus_q)
3'b011: mgt_rx_data = mgt_di_phy;
3'b101: mgt_rx_data = mgt_di_log;
3'b110: mgt_rx_data = mgt_di_usr;
default: mgt_rx_data = mgt_rx_data;
endcase
end
Change to:
always @(sel_bus_q or mgt_di_phy or mgt_di_usr or mgt_di_log)
begin
case (sel_bus_q)
3'b011: mgt_rx_data = mgt_di_phy;
3'b101: mgt_rx_data = mgt_di_log;
3'b110: mgt_rx_data = mgt_di_usr;
default: mgt_rx_data = 32'hx;
endcase
end
Revision History
04/02/2009 - Initial Release.
08/21/2009 - Add Verilog fix.