We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 32191

10.1.03 ChipScope Pro - When I use Synplify, my ChipScope Cores are removed


When I use CORE Generator and Synplify in my design, the ChipScope Cores are removed.

What is the problem? How can I work around this?


The issue in this situation is with the instantiation template generated in the <core_name>.veo. This does not specify the core as a module with the port width, input, output or inout. Synplify will trim out this kind of instantiation. For example:

chipscope_icon_v1_03_a instance_name (



To work around this issue, you can add attributes to the code generated in the <core_name>.veo and a module declaration. For example:

chipscope_icon_v1_03_a instance_name (



module chipscope_vio_v1_02_a (CLK, CONTROL, SYNC_OUT) /* synthesis syn_black_box syn_noprune=1 */;

input CLK;

inout [35 : 0] CONTROL;

output [2 : 0] SYNC_OUT;


This issue is resolved in ChipScope Pro 11.2. CORE Generator will add appropriate attributes to the example HDL files.

AR# 32191
Date Created 03/03/2009
Last Updated 12/15/2012
Status Active
Type General Article