AR #32195 - Serial RapidIO v5.2, v5.3 - Virtex-4 FXT 3.125G, 4x core might not meet timing
Serial RapidIO v5.2, v5.3 - Virtex-4 FXT 3.125G, 4x core might not meet timing
| AR# | 32195 |
| Part | IP-RapidIO-Serial |
| Last Modified | 2009-06-30 00:00:00.0 |
| Status | Active |
| Keywords | endpoint, high, speed, high-speed, PHY, logical, design environment, SRIO, RIO, rapid, IO, MGT, 11.1, I/O, Generator, physical, logicalio, transport, buffer, mgt |
Description
Keywords: endpoint, high, speed, high-speed, PHY, logical, design environment, SRIO, RIO, rapid, IO, MGT, 11.1, I/O, Generator, physical, logicalio, transport, buffer, mgt
A Serial RapidIO v5.2 or v5.3 Core generated for the Virtex-4 FXT, with x4 lanes and 3.125G line rate might fail to meet timing on the following constraints:
TS_CLK0_BUF = PERIOD TIMEGRP "CLK0_BUF".4 ns HIGH 50% INPUT_JITTER 0.1 ns PRIORITY 0
TS_UCLK = PERIOD TIMEGRP "UCLK" 6.4 ns HIGH 50% INPUT_JITTER 0.1 ns PRIORITY 0
Solution
This is scheduled to be corrected in the SRIO v5.4 core (for release with ISE 11.3).In the meantime, please contact Xilinx Technical Support for assistance:
http://www.xilinx.com/support/clearexpress/websupport.htm
Revision History
04/27/2009 - Initial Release
06/30/2009 - Updated fix schedule