This Release Note and Known Issues Answer Record is for the SPI-3 (POS-PHY L3) Physical Layer v5.2 Core, released in ISE 11.1, and contains the following information:
- New Features
- Bug Fixes
- General Information
- Known Issues
For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at:
New Features in v5.2
- ISE 11.1 software support
- Support removed for the Spartan(R)-3A DSP device family
- Tested with Virtex-5 TXT
Bug Fixes in v5.2
- Modified DCM phase shifts for select families in the sample ucf file to achieve timing closure in 11.1
- Added vsim vopt argument to ModelSim simulation scripts to prevent the tool from optimizing out unused signals that are displayed in the waveform viewer
- Version fixed: v5.2
- CR 496774
- A DCM with a PHASE_SHIFT on its clock is required to meet the OIF specification's 2 ns input timing requirement for Spartan-3/3E parts. This solution is necessary only if the system's timing budget cannot permit the PHY core to exceed the 2 ns input requirement. This constraint has been added to the design example provided with the core.
- In the example design, there are some configurations with many channels where the PHY core might fail in MAP or PAR due to either a lack of pins in the example design part or due to an inability to route to speed because of poor pin placement. This problem is due to the fact that the example design runs the backend transfer control pins to I/O, which would not necessarily be done in an actual design.
- In the example design simulation, the demo testbench might send packets to addresses beyond what the user indicated as the maximum number of channels (selected in GUI); this is not a problem because the PHY core will pass any 8-bit address through regardless of the number of channels selected (the number of channels indicates how many channels of flow control information are reported).
Known Issues in v5.2
- If the core does not meet timing with high effort for MAP and PAR, users can try running PAR with the -xe n option.
(Xilinx Answer 32503) Virtex-5 cores see PAR timing failures for polled cores