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AR# 32206

LogiCORE Ethernet 1000BASE-X PCS/PMA or SGMII v10.1 - Release Notes and Known Issues for ISE 11.1

Description

This Answer Record contains the Release Notes for the LogiCORE Ethernet 1000BASE-X PCS/PMA or SGMII v10.1 Core, which was released in the ISE 11.1 and includes the following:

- New Features

- Resolved Issues

- Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at:

http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

Solution

New Features

- ISE 11.1 software support

- Virtex-6 support

- Virtex-5 TXT support

- CR 466696 and CR 470733: the status_vector port of the core has been increased by three bits to include extra information for:

1. 8B10B decoding errors - reception of of code groups which were not recognised from the 8B10B table;

2. 8B10B decoding errors - reception of a code group with a running disparity error;

3. To include the status of the Ethernet Link as seen by the attached PHY (SGMII designs only).

- CR 471686: connected up the power down output port of the core to the powerdown input ports of Virtex-5 GTP and GTX transceivers.

- Example Design Verilog language updated to Verilog 2001 syntax, including port map definitions, use of generate statements and generic/attribute set syntax.

- Example Designs for the Virtex-4 family have been updated with new logic for the GMII and TBI physical interfaces to improve input setup/hold timing margins. The new logic now uses DCMs.

Resolved Issues

- Virtex-5 GTX VCS Verilog functional and timing simulation (Xilinx Answer 30647)

- version fixed: v10.1

- CR 467973: Virtex-5 GTX VCS verilog functional and timing simulations errored out and did not complete. This affected only simulations using GTX. It did not affect simulations using Virtex-5 GTP or Virtex-4 GT11.

- Carrier Extend assertion of odd frame length reception

- version fixed: v10.1

- CR 474938

- For reception of odd frame lengths, the GMII Carrier Extend condition was asserted for 3 clock cycles; it should have been asserted for just a single clock cycle. This behaviour was a specification compliancy issue only for an exposed GMII and would not cause interoperability issues. Additionally, when the core was attached to an internally integrated Ethernet MAC core, the system as a whole would not violate the specification. The information in Appendix D of the User Guide has been updated accordingly.

- Example Design Verilog language attribute set syntax.

- version fixed: v10.1

- CR 479876:

- The Verilog example design for designs using a Virtex-4 FX RocketIO contained attribute syntax which was reconised by XST but not by all third party synthesis tools. Where possible, standardized Verilog 2001 generics and attribute syntax are now used to overcome this problem.

- (Xilinx Answer 30577) There have been some attributes updates to the GTX wrappers since the core was released.

Known Issues

none

AR# 32206
Date Created 04/21/2009
Last Updated 12/15/2012
Status Active
Type General Article