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AR# 32210

Virtex-5 FPGA Embedded Tri-mode Ethernet MAC Wrapper v1.6 - Release Notes and Known Issues for ISE 11.1

Description

This Answer Record contains the Release Notes for the LogiCORE Embedded Tri-mode Ethernet MAC Wrapper v1.6, which was released in ISE 11.1 and includes the following:

-General Information

- New Features

- Bug Fixes

- Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at:

http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

Solution

General Information

- Supports automatic generation of HDL wrapper files for the Virtex-5 LXT Tri-Mode Ethernet MAC

- Instantiates user-configurable Ethernet MAC physical interfaces (GMII, MII, RGMII, SGMII and 1000Base-X PCS/PMA configurations are supported)

- Provides a FIFO-based example design

- Provides a demonstration testbench for the selected configuration

New Features

- ISE 11.1 software support

Resolved Issues

(Xilinx Answer 32186) 16-bit 1000BASE-X Verilog RX FIFO could incorrectly overflow.

(Xilinx Answer 31860) Virtex-4/Virtex-5 Embedded Tri-Mode Ethernet MAC - Problems switching from 10/100 Mbps to 1G GMII operation

(Xilinx Answer 30577) There have been some attributes updates to the GTX wrappers since the core was released.

- Removed PHYRESET and PHYPOWERDOWN MDIO default configuration from GUI

- See CR #471946

- These configuration values are not propagated to the wrapper files to ensure that demo testbench simulation will simulate correctly

- To change the default values of the PHYRESET and PHYPOWERDOWN MDIO configurations, users need to modify the wrapper files manually

- Wrapper files generated for Tri-Mode GMII Clock Management with Clock Enable are not consistent with Figure 6-10 of the Embedded Tri-Mode Ethernet MAC User Guide (UG194)

- See CR #501317

- Updated clock management generated by wrapper to be consistent with Figure 6-10 of UG194

- BUFG is not used to route REFCLKOUT signal from transceiver

- See CR #503642

- Update clock management generated by the wrapper for SGMII and 1000Base-X PCS/PMA configurations to route REFCLKOUT using BUFG

- This modification was made to ensure that REFCLKOUT is routed using dedicated routing and is consistent with the recommendation stated in the RocketIO GTP/GTX Transceiver User Guide

- Clarify that demo testbench disables certain default configurations when simulating irrespective of the GUI selections

- See CR #500146

- Add information in the GUI and Getting Started Guide to indicate which default configurations are disabled by the demo testbench, and hence not reflected in demo testbench simulations

Known Issues

(Xilinx Answer 32545) Virtex-5 Embedded Tri-mode Ethernet MAC Wrapper v1.6 - Implementation of GMII interface fails in MAP due to Place error

(Xilinx Answer 33456) Embedded Tri-Mode Ethernet MAC - The final byte of the Frame Check Sequence (FCS) is duplicated for some transmitted frames

(Xilinx Answer 33386) 11.3 CORE Generator software - Licenses for certain free cores are now part of the software install

(Xilinx Answer 33720) Virtex-5 FPGA Embedded Tri-mode Ethernet MAC Wrapper v1.6 - Setting Offset constraints for GMII and RGMII

AR# 32210
Date Created 04/21/2009
Last Updated 12/20/2009
Status Active
Type General Article