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AR# 32217

10.1 Timing - Why is the drive strength for Spartan-3A large at 24mA?

Description

Following are the Spartan-3A speed file delay names that get slower with higher drive strength:

D_OBUF_LVCMOS33_S2.delay 1.673 5.578 5.578

D_OBUF_LVCMOS33_S4.delay 0.950 3.165 3.165

D_OBUF_LVCMOS33_S6.delay 0.950 3.165 3.165

D_OBUF_LVCMOS33_S8.delay 0.626 2.088 2.088

D_OBUF_LVCMOS33_S12.delay 0.370 1.235 1.235

D_OBUF_LVCMOS33_S16.delay 0.345 1.150 1.150

D_OBUF_LVCMOS33_S24.delay 0.763 2.544 2.544

Following are the Spartan-3E speed file delay names that get slower with higher drive strength:

D_OBUF_LVCMOS33_S2.delay 1.321 5.071 5.282

D_OBUF_LVCMOS33_S4.delay 0.472 1.812 1.888

D_OBUF_LVCMOS33_S6.delay 0.258 0.991 1.032

D_OBUF_LVCMOS33_S8.delay 0.172 0.660 0.688

D_OBUF_LVCMOS33_S12.delay 0.103 0.396 0.412

D_OBUF_LVCMOS33_S16.delay 0.106 0.407 0.424

Why is the drive strength for Spartan-3A large at 24mA?

Solution

There are three programmable driver legs for the output pullup and pulldown with strengths 1X, 2X, and 3X. Xilinx enabled as many legs as Xilinx needed to in order to meet the drive strength requirement of any particular specification. The predrivers which drive the legs were also scaled with strength 1X, 2X, and 3X so that all three legs would turn on at the same rate.

Unfortunately, first Spartan-3A silicon failed to meet PCI66 clock-to-out. PCI66 uses clow-skew. There were two conflicting requirements, the I/O needed to be much faster, but not so fast that the slew rate would ever exceed 4v/ns (the spec for PCI66).

It was discovered that Xilinx could meet both speed and slew rate over all PVT corners if Xilinx made the 3X NMOS leg turn on slower than the 2X and 1X NMOS legs. But this would cause the kind of inconsistency in the speed files. However, only four standards use both the 3X NMOS leg and slow-slew, these are LVTTL_24_S, LVCMOS25_24_S, PCI33 and PCI66. LVTTL_24_S and LVCMOS25_24_S are only supported on banks 1 and 3.

An 'engineering' decision was made to accept two inconsistencies in order to meet PCI66 over all PVT. Fast-slew and quietIO-slew still use balanced turn-on of all three legs and should not show inconsistency in speed.

AR# 32217
Date Created 04/07/2009
Last Updated 12/15/2012
Status Active
Type General Article