11.5 AccelDSP Synthesis Tool - Why does the FFT example design fail the verify RTL step when using ISE Simulator as the HDL Simulator?

AR#	32222	Search For Another Answer
Topic	DSP Tools
Last Updated	04/14/2010
Status	Active

Description

When I run the FFT example design through the Verify -RTL stage, I receive failures and the following error messages in the simulation log: 

 #WARNING:HDLCompiler:321 - "N:/L.32/rtf/vhdl/src/simprims/primitive/other/X_ARAMB36_INTERNAL.vhd" Line 3419: Comparison between arrays of unequal length always returns FALSE. 

ERROR:Simulator:754 - Signal EXCEPTION_ACCESS_VIOLATION received

Solution

This can occur due to a known issue with the ISE Simulator. To work around this issue, you can either use a different HDL Simulator or skip this step. The problem is caused by a memory issue in the simulator.  Since AccelDSP has been discontinued in 12.1 this issue will not be resolved.