The timing error occurs for a processor clock speed of 320 MHz or greater.
To work around this problem, configure the FPU Core to:
- use pre-placed FPU = PowerPC 0
- configure FPU for high speed or low latency = High Speed
Base System Builder will be fixed in 11.2 to accommodate these design criteria. However, timing can still fail for devices containing two PowerPC embedded processor blocks, if the FPU is placed at the PowerPC location and the implementation tools place the actual PowerPC at a different location. You can place a location constraint on the PowerPC instance by taking the following steps:
1. Open the "system.ucf" file in a text editor.
2. Insert the following line at the bottom of the UCF:
Inst ppc440_0 LOC=PPC440_X0Y0;
3. Save and close the UCF.
The ppc440_0 instance name came from the "ppc440_wrapper.vhd" file. The PPC440_X0Y0 location constraint corresponds to PowerPC 0 for the FPU. Likewise, PPC440_X0Y1 corresponds to PowerPC 1 for the FPU.
The problem with Base System Builder has been fixed in EDK 11.2, available at:
http://www.xilinx.com/support/download/index.htm