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AR# 32296

LogiCORE Endpoint PIPE v1.8 for PCI Express - Core does not produce example design or simulation files when using VHDL


Known Issue: v1.8, v1.7

If the CORE Generator project is set for VHDL Design Entry, the example design files and the example simulation files are not created in the core's output directory.


As mentioned in the Getting Started Guide for the core, the example design and example simulation are provided in Verilog only. However, they can still be used with VHDL cores. To create the files, generate another core with the project set to use Verilog, then copy over the simulation, example design, and implement directories.

This is to be changed in a future release of the core so that the example files are generated for VHDL cores.

Revision History
07/23/2010 - Updated for ISE 12.1 and v1.8
03/19/2009 - Initial Release
AR# 32296
Date Created 03/23/2009
Last Updated 07/08/2010
Status Active