The Transmit LocalLink interface documented in the data sheet, DS537 released with EDK 10.1sp3 is inconsistent with the implementation.
This Answer Record provides more information on the actual implementation in the core.
Transmit LocalLink frame formatThe xps_ll_temac_v1_01_b receives data via a 32-bit wide LocalLink data bus which is in turn transmitted out as Ethernet Frames. The LocalLink bus was designed to the Xilinx LocalLink Interface Specification (SP006), which defines that the ready signals (*_RDY_n) may be used at any time to throttle data transfer as necessary. All LocalLink bus sources and destinations should be able to receive or transmit data at any time when they are indicating that they are ready and should indicate that they are not ready when they are not capable of receiving or transmitting data.
However, the xps_ll_temac_v1_01_b core's transmit LocalLink destination logic was designed to always expect 2 extra LocalLink clock cycles of "source not ready" time immediately prior to SOP going active (low). This means that although the transmit LocalLink frame is always eight 32-bit header words (words 0 to 7), the core always expects an additional 2 words after the initial 8 words during which LlinkTemac_SRC_RDY_n should be '1' (not ready).
The following figure from the xps_ll_temac data sheet is incorrect. Please refer to the second figure below for the correct representation of the LocalLink transfer.

LocalLink transfer as indicated in the data sheet
Correct representation of the LocalLink transferThe current Xilinx embedded cores drive the LocalLink bus with this same behavior, but any custom LocalLink core driving the xps_ll_temac transmit LocalLink bus must also follow this protocol. Failure to do so will result in the xps_ll_temac Core not transmitting Ethernet Frames.
The xps_ll_temac_v2_00_a Core, available in EDK 11.1i fully meets the requirements of the LocalLink standard and does not require any special LocalLink protocol work-around.