AR #32325 - 11.1 Known Issue - Timing Analysis, Virtex-5 - Why does Timing Analyzer fail to issue a Max Period Warning when I use a CRC32 component?
11.1 Known Issue - Timing Analysis, Virtex-5 - Why does Timing Analyzer fail to issue a Max Period Warning when I use a CRC32 component?
| AR# | 32325 |
| Part | SW-Timing Analyzer/TRCE |
| Last Modified | 2009-04-10 00:00:00.0 |
| Status | Active |
| Keywords | TA, TRCE, CRC, CRC64, 325MHz, 325 MHz, 270MHz, 270 MHz |
Description
Keywords: TA, TRCE, CRC, CRC64, 325MHz, 325 MHz, 270MHz, 270 MHz
Why does Timing Analyzer fail to issue a Max Period Warning when I use a CRC32 component?
Solution
This is an issue with Timing Analyzer; the CRC components characterization information is not available to TRACE, consequently, TRACE is unable to check against the allowed operating frequencies of the CRC components.Please follow the specifications outlined in the "Virtex-5 FPGA Data Sheet: DC and Switching Characteristics Product Specification (DS202):
http://www.xilinx.com/support/documentation/data_sheets/ds202.pdf