When I generate my System Generator for DSP design with "Create Testbench" enabled, the resulting testbench does not work if my design contains an EDK Processor block. Why?
This is because simulation of the EDK Processor block is not supported; therefore, a testbench cannot be accurately created.
The "Create Testbench" option should not be used with designs containing the EDK Processor block.
Additionally, the "vcom.do" file which can be created regardless of the "Create Testbench" option, does not contain a comprehensive compilation list for the same reasons mentioned above.