AR #32375 - MIG 2.3/3.0/3.1, Virtex-5 QDRII - Potential for small margin between the CQ and FPGA clock after stage 2 calibration for frequencies between 125 - 250 MHz
MIG 2.3/3.0/3.1, Virtex-5 QDRII - Potential for small margin between the CQ and FPGA clock after stage 2 calibration for frequencies between 125 - 250 MHz
| AR# | 32375 |
| Part | IP-MIG-QDR II SRAM |
| Last Modified | 2009-09-10 00:00:00.0 |
| Status | Active |
| Keywords | MIG, Virtex-5, QDRII, calibration, fail, max_window, stage, rd_data_rise, rd_data_fall |
Description
Keywords: MIG, Virtex-5, QDRII, calibration, fail, max_window, stage, rd_data_rise, rd_data_fall
The Virtex-5 QDRII design aligns CQ/Q to the FPGA clock during stage 2 of calibration. The algorithm assigns a minimum window requirement based on the target frequency. For frequencies above 250 MHz, this limit is set to 15. For frequencies below 250 MHz, this limit is set to 20.
There is a potential, when running at frequencies below 250 MHz, for the CQ/Q and FPGA clock to not be 20 taps apart (the minimum window requirement). This results in an inaccurate completion of stage 2 calibration with insufficient margin between the FPGA clock and CQ/Q.
The design could potentially pass calibration; however, there might not be sufficient margin left between the two clocks. Over voltage-temperature changes, this insufficient margin might show up as data errors.
Solution
To work around this issue, changes are required to the phy_dly_cal_sm.v/.vhd module that ensure CQ/Q and the FPGA clock (CLK0) will always be more than 20 taps apart.Please download the phy_dly_cal_sm.v/.vhd file from the following link:
ftp://ftp.xilinx.com/pub/applications/misc/ar32375.zip
The file downloaded should then be used in place of the phy_dly_cal_sm.v/.vhd module provided with the MIG output.
This issue will be resolved in MIG 3.2.